Victor Wanderley Costa de Medeiros

Bio: Victor Wanderley Costa de Medeiros is an academic researcher from Universidade Federal Rural de Pernambuco. The author has contributed to research in topics: Field-programmable gate array & General-purpose computing on graphics processing units. The author has an hindex of 4, co-authored 22 publications receiving 40 citations. Previous affiliations of Victor Wanderley Costa de Medeiros include Universidade de Pernambuco & Federal University of Pernambuco.

Design and implementation of an electronic nose system for real-time detection of marijuana

Abstract: Rapid and sensitive identification of illicit drugs has been a challenge and requires new methods. This study proposes a newly developed electronic nose (e-nose) based on commercially available gas...

Energy Estimation Tool FPGA-based Approach for Petroleum Industry

Abstract: Energy consumption is one of the great villains in high-performance processing when applied to large clusters that continuously run certain applications. Seismic migration applications are targets of this type of processing, since this feature denotes a need to apply complex models that are continuously run to evaluate drilling of petroleum wells. This work describes an analysis tool of energy consumption of a seismic application applied to FPGA architecture for a real Brazilian industry. A comparative study with the traditional multi-core and with GPGPU architectures is performed and results indicate an increase in efficiency/Joule of about 23 and 1.5 times higher respectively. Experiments performed with the Marmousi model revels an error about 3.7% when compared with measured values.

Exploiting Heterogeneous Computing Platforms By Cataloging Best Solutions For Resource Intensive Seismic Applications

Abstract: Large heterogeneous data centers of today lack methods to appraise the best fitting solutions regarding, among others, hardware acquisition cost, development time, and performance. Especially resource intensive applications benefit from increased data center utilization to leverage heterog eneous resources and accelerators. In this paper, we implement var ious methods to accelerate a seismic modeling application, whic h is available for CPU, GPU, and FPGA. With the underlying heterogeneous environment, the current programming standard OpenCL is examined regarding CPUs and GPUs, and compared to traditional acceleration approaches in order t o evaluate sets of platforms. Based on the variety of availabl e versions, a flow is introduced, which allows to catalog best solu tions by experimenting with different implementations for available hardware platforms. We encourage to derive indicators as hi nts for data center operators with respect to finding a cost-bene fit trade-off, which must also be observed over time. The result s highlight the GPU and FPGA implementations, and correlate performance optimizations with development time, regardi ng the seismic application and the underlying hardware platforms. Keywords-heterogeneous computing platform, accelerator, seismic exploration, OpenCL, CPU, GPU, FPGA

FPGA-based architecture to speed-up scientific computation in seismic applications

Abstract: Hardware accelerators like GPGPUs and FPGAs have been used as an alternative to conventional CPU architectures in scientific computing applications and have shown considerable speed-ups on them. In this context, this work presents an FPGA-based solution that explores efficiently the data reuse and spatial and time domain parallelism for the first computational stage of the reverse time migration (RTM) algorithm, the seismic modelling. We also implemented the same algorithm for some CPUs and GPGPU architectures and our results showed that an FPGA-based approach can be a feasible solution to improve performance. Experimental results showed similar performance when compared to the GPGPU and up to 28.91 times speed-up when compared to CPUs. In terms of energy efficiency, the FPGA is almost 23 times and 1.75 times more efficient than the CPU and GPGPU, respectively. We also discuss some other features and possible optimisations that can be included in the proposed architecture that can make this performance even better.

Reconfigurable Computing. Accelerating Computation with Field-Programmable Gate Arrays

Abstract: Reconfigurable Computing. Accelerating Computation with Field-Programmable Gate Arrays by Maya B. Gokhale and Paul S. Graham Springer, 2005, 238 pp. ISBN-13 978-0387-26105-8, $87.20 Reconfigurable Computing Accelerating Computation with Field-Programmable Gate Arrays is an expository and easy to digest book. The authors are recognized leaders with many years of experience on the field of reconfigurable computing. The book is written so that non-specialists can understand the principles, techniques and algorithms. Each chapter has many excellent references for interested readers. It surveys methods, algorithms, programming languages and applications targeted to reconfigurable computing. Automatic generation of parallel code from a sequential program on conventional micro-processor architectures remains an open problem. Nevertheless, a wide range of computationally intensive applications have benefited from many tools developed to tackle such a problem. For RC, it is even a much harder problem (perhaps 10x and up) and intense research is being devoted to make RC a common-place practical tool. The aim of the authors is threefold. First, guide the readers to know current issues on HLL for RC. Second, help the readers understand the intricate process of algorithmic-to-hardware compilation. And third, show that, even though this process is painful, if the application is suitable for RC the gains in performance are huge. The book is divided into two parts. The first part contains four chapters about reconfigurable computing and languages. Chapter 1 presents an introduction of RC, contrasting conventional fixed instruction microprocessors with RC architectures. This chapter also contains comprehensive reference material for further reading. Chapter 2 introduces reconfigurable logic devices by explaining the basic architecture and configuration of FPGAs. Chapter 3 deals with RC systems by discussing how parallel processing is achieved on reconfigurable computers and also gives a survey of RC systems today. Then, in chapter 4, languages, compilation, debugging and their related manual vs. automatic issues are discussed. The second part of the book comprises five chapters about applications of RC. Chapter 5 and 6 discuss digital signal and image processing applications. Chapter 7 covers the application of RC to secure network communications. The aim of Chapter 8 is to discuss some important bioinformatics applications for which RC is a good candidate, their algorithmic problems and hardware implementations. Finally, Chapter 9 covers two applications of reconfigurable supercomputers. The first one is a simulation of radiative heat transfer and the second one models large urban road traffic. This book is neither a technical nor a text book, but in the opinion of this reviewer, it is an excellent state-of-the-art review of RC and would be a worthwhile acquisition by anyone seriously considering speeding up a specific application. On the downside, it is somewhat disappointing that the book does not contain more information about HLL tools that could be used to help close the gap between traditional HPC community and the raw computing power of RC. Edusmildo Orozco, Department of Computer Science, University Of Puerto Rico at Rio Piedras.