Algorithms for face detection in an image find their usage in a wide range of industrial applications. In this paper, a popular Viola-Jones algorithm for face detection is described using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The proposed digital design is synthesized and implemented in ZYBO ZYNQ 7010 System on Chip (SoC) FPGA. The proposed design can process different image resolutions with minimal changes in the design. The evaluation of the proposed solution confirms the correctness of the implementation and possibility to use the proposed design in many applications requiring cost-efficient and real-time face detection.

Face Detection in Images Using an FPGA

Face Detection is a process of finding whether there are faces present in an image. This process needs large amount of information processing and thus, results in poor performance when performed on general purpose CPU. The main objective of this paper is implement a hardware based face detection system on Field Programmable Gate Array (FPGA) using VHDL. Also, the goal is to carry a comparative analysis of Viola-Jones face detection algorithm being implemented on Altera DE2-115 FPGA board and MATLAB simulation tool on the basis of processing time and cost.

Performance of Viola-Jones Algorithm Using Matlab and FPGA for Hardware Acceleration

The gas distribution system is used to transfer gas from one place to another. Here, explosion takes place when cracks are present in pipeline. In our project, the main objective is to determine the precise location of cracks present in underground pipelines so that human efforts and financial loses can be reduced. To detect the cracks, robot is used to detect the cracks with the help of ultrasonic sensor. Two dc gear motors of 300 rpm are used for movement of robot. The whole setup is interfaced with Nexys4 using FPGA. Ultrasonic sensor transmits eight 40 KHz ultrasonic burst to inner surface of pipe. The pipe then reflects ultrasonic burst and ECHO signal is in high state. In absence of cracks, ECHO pulse width ranges from 150us to 20us and in presence of cracks, ECHO pulse width is beyond 25ms. LCD in user module displays "crack" or "no crack" depending upon the data received. The whole setup consists of Nexys-4, ultrasonic sensor, LCD, DC motors which are implemented on FPGA due to its reconfigurable nature, low price and marketing speed.

Vidhyapathi C M

Papers

Performance of Viola-Jones Algorithm Using Matlab and FPGA for Hardware Acceleration

Crack Detection Robot in Underground Gas Pipelines using FPGA