Vijender Kumar Sharma

Bio: Vijender Kumar Sharma is an academic researcher from Indian Institute of Technology Mandi. The author has contributed to research in topics: Jitter & Buck converter. The author has an hindex of 5, co-authored 17 publications receiving 66 citations. Previous affiliations of Vijender Kumar Sharma include Indraprastha Institute of Information Technology.

A Review on Power Supply Induced Jitter

Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

An analysis of power supply induced jitter for a voltage mode driver in high speed serial links

Abstract: Estimation of jitter in early design cycle of an SoC is necessary to avoid jitter budget conflicts in the design. In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed. The circuit used for the analysis is designed in 28nm FD-SOI technology but the analysis is technology independent. Jitter induced by noise in power delivery networks is analyzed by a transfer function from power supply to the output by a small signal equivalent model. The analysis can be extended generically for System-On-Chip (SoC) level design considerations.

A comparative analysis of jitter estimation techniques

Abstract: With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

Abstract: This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

Abstract: This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.

The Design and Analysis of Experiments

Abstract: THE DESIGN AND ANALYSIS OF EXPERIMENTS. By Oscar Kempthorne. New York, John Wiley and Sons, Inc., 1952. 631 pp. $8.50. This book by a teacher of statistics (as well as a consultant for \"experimenters\") is a comprehensive study of the philosophical background for the statistical design of experiment. It is necessary to have some facility with algebraic notation and manipulation to be able to use the volume intelligently. The problems are presented from the theoretical point of view, without such practical examples as would be helpful for those not acquainted with mathematics. The mathematical justification for the techniques is given. As a somewhat advanced treatment of the design and analysis of experiments, this volume will be interesting and helpful for many who approach statistics theoretically as well as practically. With emphasis on the \"why,\" and with description given broadly, the author relates the subject matter to the general theory of statistics and to the general problem of experimental inference. MARGARET J. ROBERTSON

Logical Effort Designing Fast Cmos Circuits

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A Review on Power Supply Induced Jitter

Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

Efficient Jitter Analysis for a Chain of CMOS Inverters

Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.