Vijeyakumar Krishnasamy Natarajan

Bio: Vijeyakumar Krishnasamy Natarajan is an academic researcher from Dr. Mahalingam College of Engineering and Technology. The author has contributed to research in topics: Adder & Multiplier (economics). The author has an hindex of 2, co-authored 4 publications receiving 17 citations.

Area-efficient parallel adder with faithful approximation for image and signal processing applications

Abstract: Design of low-power and area-efficient portable complementary metal–oxide–semiconductor processors for image and signal processing applications demand reduction in transistor switching and count. Adder is the fundamental block of all arithmetic operations performed in processing units. In this study, an error-tolerant parallel adder with faithful approximation is proposed that can optimise area and accuracy. In the proposed parallel adder, for n bit input and m bit adder block, least n/2m blocks are designed with approximate logic using carry by-pass addition algorithm and most n/2m blocks are designed with exact logic using carry select addition algorithm. Least significant approximate part of the adder is designed with either exact full adder (EFA) or fault-tolerant full adder (FTFA) cells. This confines the maximum error in the proposed-EFA and proposed-FTFA designs to be not more than unit bit value with weights 2[(n/2m)−1]m and 2 n /2, respectively. Two different FTFA cells are proposed and implemented in the approximate blocks. The synthesis results of the proposed-EFA, proposed-FTFA1 and proposed-FTFA2 designs using Cadence Encounter with 90 nm ASIC technology for n = 16, m = 4 demonstrated an area saving of 22.3, 28.2 and 35%, respectively, when compared to the conventional counterpart.

Area–Energy–Error Optimized Faithful Multiplier for Digital Signal Processing

Abstract: Approximate computing is a striking approach to design area-efficient low-power datapath units for fault buoyant applications. This brief presents the design of a novel 4: 2 approximate compressor that generates no error in the carry signal. The proposed compressor is employed for partial product (PP) compression in two variants of Dadda multiplier to see its effectiveness in error-resilient image and signal processing applications. In the targeted multipliers, the approximate 4:2 compressor is used in the least n PP columns, while the exact counterpart is used in the remaining most significant columns, and hence the maximum error is precisely maintained within 2n. PP compression is performed in stages using the Wallace approach, and the final two rows of sum and carry signals are added using a ripple carry adder in the basic design. In the proposed multiplier design-2, we do not generate sum bits in the approximate part. However, the proposed error-tolerant compressor is used in appropriate columns to propagate carry to the least significant column in the exact part. Performance evaluations using Cadence Encounter with 90 nm application specific integrated circuit technology revealed that the proposed-full width (P-FW) and the proposed-truncated (P-Trun) approximate multipliers demonstrate 22.7% and 32.4% power-delay product reduction compared to the standard multiplier. Implementations of the proposed multipliers in signal and image processing applications revealed superior performance in terms of accuracy compared to prior similar approximate designs.

Design of Efficient Reversible BCD Adder–Subtractor Architecture and Its Optimization Using Carry Skip Logic

Abstract: In the present era, reversible logic designs play a very critical role in nanotechnology, low power complementary metal-oxide semiconductor (CMOS) designs, optical computing and, especially, in quantum computing. High power dissipation and leakage current in deep submicron technologies is a severe threat in applications created today. As a consequence, design of datapath elements in reversible logic has gained much importance. In this study, a novel design of binary coded decimal (BCD) adder/subtractor in reversible logic has been proposed. As a further optimization of the proposed reversible decimal design, carry skip (CSK) logic is used for reversible ripple carry adder stages. This reduces delay but at the expense of little hardware. The proposed BCD adder/subtractor and its optimized version are designed using structural VHDL and simulated using ModelSim 6.3f. Performance analysis reveals that the proposed BCD design demonstrates reductions in gate count, garbage outputs and constant inputs of 30.5%, 46% and 28%, respectively, and its optimized version exhibits 19.4%, 32.4% and 16% reductions in gate count, garbage outputs and constant inputs compared to the design in Ref. 14 [V. Rajmohan, V. Renganathan and M. Rajmohan, A novel reversible design of unified single digit BCD adder–subtractor, Int. J. Comput. Theor. Eng. 3 (2011) 697–700].

Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing

Abstract: In the recent years, error recovery circuits in optimized data path units are adopted with approximate computing methodology. In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum (ES) and Error free Carry (EC). Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product (PP) compression. The structural arrangement utilizes Dadda structure based PP. Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design. In this, the proposed compression idealogy are more effective in the smallest n columns, and the accurate compressor in the remaining most significant columns. This limits the error in the multiplier output to be not more than 2 for an n X n multiplication. The choice among the proposed compressors is decided based on the significance of the sum and carry signals on the multiplier result. As an enhancement to the proposed multiplier, we introduce two Area Efficient (AE) variants viz., Proposed-AE (P-AE), and P-AE with Error Recovery (P-AEER). The proposed basic P-AE, and P-AEER designs exhibit 46.7%, 52.9%, and 52.7% PDP reduction respectively when compared to an approximate multiplier of minimal error type and are designed with 90nm ASIC technology. The proposed design and their performance validation are done by using Cadence Encounter. The performance evaluations are carried out using cadence encounter with 90nm ASIC technology. The proposed-basic P-AEA and P-AEER designs demonstrate 46.7%, 52.9% and 52.7% PDP reduction compared to the minimal error approximate multiplier. The proposed multiplier is implemented in digital image processing which revealed 0.9810 Structural SIMilarity Index (SSIM), to the least, and less than 3% deviation in ECG signal processing application.

Implementation of FPGA design of FFT architecture based on CORDIC algorithm

Abstract: The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of converge...

Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation

Abstract: In every modern ICs the adders are essential components. Adder’s performance has a terrific impact on the architecture of signal processing, controller, the module of filter, the module of data storage, etc., high-speed and area-efficient circuits are the most substantial parameters in every modern integrated circuit. Carry select adder operates at high speed, but it consumes more power due to the large area. The present approach discloses different VLSI hybrid carry select adder architectures. The hybrid technology-based Carry Select adder (CSELA) consists of two stages, namely the Hancarlson adder stage and Hybrid Stage is proposed. In this technique, all the stages (4 bits in each stage) are performed simultaneously to improve the speed and area further. The propagation delays of the proposed adder are the summation of two full adders, seven Multiplexers (4:1) and BEC(3 bit) for producing Cout. The proposed work indicates that the hybrid carry select adder operates at high a speed with a lesser area than the conventional adder. The proposed design is simulated and synthesized in Xilinx ISE 12.1 using Verilog HDL with a family of Vertex6 FPGA devices (Device No. XC6VLX75T, Package FF484, Speed -3). The synthesized report shows that the speed of the proposed adder is improved by 49.06%, 52.61%, 47.58%, 19.08%, 39.9%, 1.25%, 44.43%,19.08%, 44.07% and 71.59% compared to RCA, CBL-based CSELA, CLA, Weinberger BEC-based CSELA,D latched CSELA, Brent Kung CSELA, Brent Kung RCA-based CSELA, CSA Weinberger, Conventional CSELA and Ling CSELA, respectively.