Viktor Schuppan

Bio: Viktor Schuppan is an academic researcher. The author has contributed to research in topics: Model checking & Conjunctive normal form. The author has an hindex of 1, co-authored 1 publications receiving 28 citations.

Towards a notion of unsatisfiable cores for LTL

Abstract: Unsatisfiable cores, i.e., parts of an unsatisfiable formula that are themselves unsatisfiable, have important uses in debugging specifications, speeding up search in model checking or SMT, and generating certificates of unsatisfiability. While unsatisfiable cores have been well investigated for Boolean SAT and constraint programming, the notion of unsatisfiable cores for temporal logics such as LTL has not received much attention. In this paper we investigate notions of unsatisfiable cores for LTL that arise from the syntax tree of an LTL formula, from converting it into a conjunctive normal form, and from proofs of its unsatisfiability. The resulting notions are more fine-granular than existing ones.

Theory and applications of satisfiability testing - SAT 2007 : 10th International Conference, Lisbon, Portugal, May 28-31, 2007 : proceedings

Abstract: SAT: Past and Future.- Encodings of Problems in Effectively Propositional Logic.- Efficient Circuit to CNF Conversion.- Mapping CSP into Many-Valued SAT.- Circuit Based Encoding of CNF Formula.- Breaking Symmetries in SAT Matrix Models.- Partial Max-SAT Solvers with Clause Learning.- MiniMaxSat: A New Weighted Max-SAT Solver.- Solving Multi-objective Pseudo-Boolean Problems.- Improved Lower Bounds for Tree-Like Resolution over Linear Inequalities.- Horn Upper Bounds and Renaming.- Matched Formulas and Backdoor Sets.- Short XORs for Model Counting: From Theory to Practice.- Variable Dependency in Local Search: Prevention Is Better Than Cure.- Combining Adaptive Noise and Look-Ahead in Local Search for SAT.- From Idempotent Generalized Boolean Assignments to Multi-bit Search.- Satisfiability with Exponential Families.- Formalizing Dangerous SAT Encodings.- Algorithms for Variable-Weighted 2-SAT and Dual Problems.- On the Boolean Connectivity Problem for Horn Relations.- A First Step Towards a Unified Proof Checker for QBF.- Dynamically Partitioning for Solving QBF.- Backdoor Sets of Quantified Boolean Formulas.- Bounded Universal Expansion for Preprocessing QBF.- Effective Incorporation of Double Look-Ahead Procedures.- Applying Logic Synthesis for Speeding Up SAT.- Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver.- A Lightweight Component Caching Scheme for Satisfiability Solvers.- Minimum 2CNF Resolution Refutations in Polynomial Time.- Polynomial Time SAT Decision for Complementation-Invariant Clause-Sets, and Sign-non-Singular Matrices.- Verifying Propositional Unsatisfiability: Pitfalls to Avoid.- A Simple and Flexible Way of Computing Small Unsatisfiable Cores in SAT Modulo Theories.- SAT Solving for Termination Analysis with Polynomial Interpretations.- Fault Localization and Correction with QBF.- Sensor Deployment for Failure Diagnosis in Networked Aerial Robots: A Satisfiability-Based Approach.- Inversion Attacks on Secure Hash Functions Using sat Solvers.

FM 2008 : formal methods : 15th International Symposium on Formal Methods, Turku, Finland, May 26-30, 2008 : proceedings

Abstract: Session 1. Invited Talks.- Aspects and Formal Methods.- Getting Formal Verification into Design Flow.- Lessons in the Weird and Unexpected: Some Experiences from Checking Large Real Systems.- Simulation, Orchestration and Logical Clocks.- Session 2. Programming Language Analysis.- CoVaC: Compiler Validation by Program Analysis of the Cross-Product.- Lazy Behavioral Subtyping.- Checking Well-Formedness of Pure-Method Specifications.- Session 3. Verification.- Verifying Dynamic Pointer-Manipulating Threads.- Proofs and Refutations for Probabilistic Refinement.- Assume-Guarantee Verification for Interface Automata.- Session 4. Real-Time and Concurrency.- Automated Verification of Dense-Time MTL Specifications Via Discrete-Time Approximation.- A Model Checking Language for Concurrent Value-Passing Systems.- Session 5. Grand Chellenge Problems.- Verification of Mondex Electronic Purses with KIV: From a Security Protocol to Verified Code.- Incremental Development of a Distributed Real-Time Model of a Cardiac Pacing System Using VDM.- Session 6. FM Practice.- Industrial Use of Formal Methods for a High-Level Security Evaluation.- Secret Ninja Formal Methods.- Specification and Checking of Software Contracts for Conditional Information Flow.- Session 7. Runtime Moitoring and Analysis.- JML Runtime Assertion Checking: Improved Error Reporting and Efficiency Using Strong Validity.- Provably Correct Runtime Monitoring.- Session 8. Communication.- A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS.- A Rigorous Approach to Networking: TCP, from Implementation to Protocol to Service.- Session 9. Constraint Analysis.- Constraint Prioritization for Efficient Analysis of Declarative Models.- Finding Minimal Unsatisfiable Cores of Declarative Specifications.- Precise Interval Analysis vs. Parity Games.- Session 10. Design.- Introducing Objects through Refinement.- Masking Faults While Providing Bounded-Time Phased Recovery.- Towards Consistent Specifications of Product Families.- Session 11. Industry Day.- Formal Methods for Trustworthy Skies: Building Confidence in the Security of Aircraft Assets Distribution.- An Industrial Case: Pitfalls and Benefits of Applying Formal Methods to the Development of a Network-Centric RTOS.- Software Engineering with Formal Methods: Experiences with the Development of a Storm Surge Barrier Control System.- Application of a Formal Specification Language in the Development of the "Mobile FeliCa" IC Chip Firmware for Embedding in Mobile Phone.- Safe and Reliable Metro Platform Screen Doors Control/Command Systems.

Explaining Impossible High-Level Robot Behaviors

Abstract: A key challenge in robotics is the generation of controllers for autonomous, high-level robot behaviors comprising nontrivial sequences of actions, including reactive and repeated tasks. When constructing controllers to fulfill such tasks, it is often not known a priori whether the intended behavior is even feasible; plans are modified on the fly to deal with failures that occur during execution, often still without guaranteeing correct behavior. Recently, formal methods have emerged as a powerful tool to automatically generate autonomous robot controllers that guarantee desired behaviors expressed by a class of temporal logic specifications. However, when the specification cannot be fulfilled, these approaches do not provide the user with a source of failure, making the troubleshooting of specifications an unstructured and time-consuming process. This paper describes an algorithm to automatically analyze an unsynthesizable specification in order to identify causes of failure. It also introduces an interactive game to explore possible causes of unsynthesizability, in which the user attempts to fulfill the robot specification against an adversarial environment. The proposed algorithm and game are implemented as features within the LTLMoP toolkit for robot mission planning.

Analyzing unsynthesizable specifications for high-level robot behavior using LTLMoP

Abstract: Recent work in robotics has applied formal verification tools to automatically generate correct-by-construction controllers for autonomous robots. However, when it is not possible to create such a controller, these approaches do not provide the user with feedback on the source of failure, making the experience of debugging a specification somewhat ad hoc and unstructured, and a source of frustration for the user. This paper describes an extension to the LTLMoP toolkit for robot mission planning that encloses the control-generation process in a layer of automated reasoning to identify the cause of failure, and targets the users attention to flawed portions of the specification.

Diagnosis and Repair for Synthesis from Signal Temporal Logic Specifications

Abstract: We address the problem of diagnosing and repairing specifications for hybrid systems, formalized in signal temporal logic (STL). Our focus is on automatic synthesis of controllers from specifications using model predictive control. We build on recent approaches that reduce the controller synthesis problem to solving one or more mixed integer linear programs (MILPs), where infeasibility of an MILP usually indicates unrealizability of the controller synthesis problem. Given an infeasible STL synthesis problem, we present algorithms that provide feedback on the reasons for unrealizability, and suggestions for making it realizable. Our algorithms are sound and complete relative to the synthesis algorithm, i.e., they provide a diagnosis that makes the synthesis problem infeasible, and always terminate with a non-trivial specification that is feasible using the chosen synthesis method, when such a solution exists. We demonstrate the effectiveness of our approach on controller synthesis for various cyber-physical systems, including an autonomous driving application and an aircraft electric power system.