Viktor Sverdlov

Bio: Viktor Sverdlov is an academic researcher from Vienna University of Technology. The author has contributed to research in topics: Magnetoresistive random-access memory & Spin-transfer torque. The author has an hindex of 21, co-authored 249 publications receiving 2008 citations. Previous affiliations of Viktor Sverdlov include University of Vienna & University of Geneva.

The Effect of General Strain on the Band Structure and Electron Mobility of Silicon

Abstract: A model capturing the effect of general strain on the electron effective masses and band-edge energies of the lowest conduction band of silicon is developed. Analytical expressions for the effective mass change induced by shear strain and valley shifts/splittings are derived using a degenerate kldrp theory at the zone-boundary X point. Good agreement to numerical band- structure calculations using the nonlocal empirical pseudopotential method with spin-orbit interactions is observed. The model is validated by calculating the bulk electron mobility under general strain with a Monte Carlo technique using the full-band structure and the proposed analytical model for the band structure. Finally, the impact of strain on the inversion-layer mobility of electrons is discussed.

The Universality of NBTI Relaxation and its Implications for Modeling and Characterization

Abstract: As of date many NBTI models have been published which aim to successfully capture the essential physics. As such, these models have mostly focused on the stress phase. The relaxation phase, on the other hand, has not received as much attention, possibly because of the contradictory results published so far. Particularly noteworthy are the very long relaxation tails of almost logarithmic nature, which cannot be successfully described by the reaction-diffusion model. The authors argue that understanding the nature of the relaxation phase could hold the key to unraveling the underlying NBTI mechanism. In particular, the authors stipulate that the relaxation phase follows a universal relaxation law, demonstrate the valuable consequences resulting therefrom, and use this universality to classify presently available NBTI models.

CMOS-compatible spintronic devices: a review

Abstract: For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wallmotion MRAM, and spin–orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOScompatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Nanoscale silicon MOSFETs: A theoretical study

Abstract: We have carried out extensive numerical modeling of double-gate, nanoscale silicon n-metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin, intrinsic channels connecting bulk, highly doped electrodes. Our model takes into account two most important factors limiting the device performance as the gate length is reduced, namely the gate field screening by source and drain, and quantum mechanical tunneling from source to drain. The results show that the devices with small but plausible values of gate oxide thickness t/sub ox/ and channel thickness t (both of the order of 2 nm) may retain high ON current, good saturation and acceptable subthreshold slope even if the gate length L is as small as /spl sim/5 nm, with voltage gain above unity all the way down to L/spl ap/2 nm (channel length L/sub c/=L+2t/sub ox//spl ap/5 nm). However, as soon as L is decreased below /spl sim/10 nm, specific power (per unit channel width) starts to grow rapidly. Even more importantly, threshold voltage becomes an extremely sensitive function of L,t, and t/sub ox/, creating serious problems for reproducible device fabrication.

In-memory computing with resistive switching devices

Abstract: Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing. This Review Article examines the development of in-memory computing using resistive switching devices.

Electronic structure of quantum dots

Abstract: The properties of quasi-two-dimensional semiconductor quantum dots are reviewed. Experimental techniques for measuring the electronic shell structure and the effect of magnetic fields are briefly described. The electronic structure is analyzed in terms of simple single-particle models, density-functional theory, and "exact" diagonalization methods. The spontaneous magnetization due to Hund's rule, spin-density wave states, and electron localization are addressed. As a function of the magnetic field, the electronic structure goes through several phases with qualitatively different properties. The formation of the so-called maximum-density droplet and its edge reconstruction is discussed, and the regime of strong magnetic fields in finite dot is examined. In addition, quasi-one-dimensional rings, deformed dots, and dot molecules are considered. (Less)