Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the complementary metal-oxide-semiconductor (CMOS) roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time, and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.

Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Tunnel Field-Effect Transistors: Prospects and Challenges

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.

The era of hyper-scaling in electronics

Sooner or later, fundamental limitations destine complementary metal-oxide-semiconductor (CMOS) scaling to a conclusion. A number of unique switches have been proposed as replacements, many of which do not even use electron charge as the state variable. Instead, these nanoscale structures pass tokens in the spin, excitonic, photonic, magnetic, quantum, or even heat domains. Emergent physical behaviors and idiosyncrasies of these novel switches can complement the execution of specific algorithms or workloads by enabling quite unique architectures. Ultimately, exploiting these unusual responses will extend throughput in high-performance computing. Alternative tokens also require new transport mechanisms to replace the conventional chip wire interconnect schemes of charge-based computing. New intrinsic limits to scaling in post-CMOS technologies are likely to be bounded ultimately by thermodynamic entropy and Shannon noise.

Device and Architecture Outlook for Beyond CMOS Switches

Steep sub-threshold Interband Tunnel FETs (TFETs) are promising candidates for low supply voltage applications with higher switching performance than traditional CMOS. Unlike CMOS, TFETs exhibit uni-directional conduction due to their asymmetric source-drain architecture, and delayed output saturation characteristics. These unconventional characteristics of TFETs pose a challenge for providing good read/write noise margin characteristics in TFET SRAMs. We provide an analysis of 8T and 10T TFET SRAM cells, including Schmitt-Trigger (ST) based cells, to address these shortcomings. By benchmarking a variety of TFET-based SRAM cells, we show the utility of the Schmitt-Trigger feedback mechanism in improving the read/write noise margins, thus enabling ultra low-V CC operation for TFET SRAMs. We also propose a variation model for studying the impact of device-level variation on TFET SRAM cells. We show that the TFET ST SRAM cell has sufficient variation tolerance to operate at low-V CC , and is a very promising cell to achieve a V CC -min of 124mV. The TFET ST cell operating at its V CC -min provides a 1.2x reduction in dynamic energy and 13x reduction in leakage power compared to the best CMOS-based SRAM implementation operating at it's V CC -min, while giving better performance at the same time.

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Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

The steep sub-threshold characteristics of inter-band tunneling FETs (TFETs) make an attractive choice for low voltage operations. In this work, we propose a hybrid TFET-CMOS chip multiprocessor (CMP) that uses CMOS cores for higher voltages and TFETs for lower voltages by exploiting differences in application characteristics. Building from the device characterization to design and simulation of TFET based circuits, our work culminates with a workload evaluation of various single/multi-threaded applications. Our evaluation shows the promise of a new dimension to heterogeneous CMPs to achieve significant energy efficiencies (upto 50% energy benefit and 25% ED benefit with single-threaded applications, and 55% ED benefit with multi-threaded applications).

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An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores

Heterogeneous multicores are envisioned to be a promising design paradigm to combat today's challenges of power, memory, and reliability walls that are impeding chip design using deep submicron technology. Future multicores are expected to integrate multiple different cores, including GPGPUs, custom accelerators and configurable cores. In this paper, we introduce an important dimension-technology-using which heterogeneity can be introduced in multicores to improve their energy-performance envelope. Specifically, we analyze the benefits of heterogenous technologies for processor cores and cache subsystems. We discuss two promising device candidates (Tunnel-FET and Magnetic-RAM) for introducing technological diversity in the multicores and analyze their integration in the processor and cache hierarchy in detail. Our analysis shows that introducing such a kind of heterogeneity can significantly enhance the performance and energy behavior of future multicore systems.

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors

Although the superior subthreshold characteristics of steep-slope devices can help power up more cores, researchers still need CMOS technology to accelerate sequential applications, because it can reach higher frequencies. Device-level heterogeneous multicores can give the best of both worlds, but they need smart resource management to realize this promise. In this article, the authors discuss device-level heterogeneous multicores and various resource-management schemes for reaching higher energy efficiency.

Steep-Slope Devices: From Dark to Dim Silicon

The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device - the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.

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Vinay Saripalli

Papers

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors

Steep-Slope Devices: From Dark to Dim Silicon

Ultra Low Power Circuit Design Using Tunnel FETs