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Vincent J. Mooney

Bio: Vincent J. Mooney is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Software & Cache. The author has an hindex of 28, co-authored 109 publications receiving 2494 citations. Previous affiliations of Vincent J. Mooney include Nanyang Technological University & Stanford University.


Papers
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Proceedings ArticleDOI
02 Oct 2002
TL;DR: The automated generation of a round-robin token passing BA to reduce time spent on arbiter design and the design and integration of a distributed fast arbiter, e.g., for a terabit switch, based on 2/spl times/2 and 4/ spl times/4 switch arbiters (SAs).
Abstract: In this paper, we introduce a Round-robin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of bus masters for both on-chip and off-chip buses. RAG can also generate a distributed and parallel hierarchical Switch Arbiter (SA). The first contribution of this paper is the automated generation of a round-robin token passing BA to reduce time spent on arbiter design. The generated arbiter is fair, fast, and has a low and predictable worst-case wait time. The second contribution of this paper is the design and integration of a distributed fast arbiter, e.g., for a terabit switch, based on 2/spl times/2 and 4/spl times/4 switch arbiters (SAs). Using a .25/spl mu/ TSMC standard cell library from LEDA Systems [10, 14], we show the arbitration time of a 256/spl times/256 SA for a terabit switch and demonstrate that the SA generated by RAG meets the time constraint to achieve approximately six terabits of throughput in a typical network switch design. Furthermore, our generated SA performs better than the Ping-Pong Arbiter and Programmable Priority Encoder by a factor of 1.9/spl times/ and 2.4/spl times/, respectively.

165 citations

Journal ArticleDOI
TL;DR: The sleepy stack technique achieves the lowest leakage power consumption among known state-saving leakage reduction techniques, thus, providing circuit designers with new choices to handle the leakage power problem.
Abstract: Leakage power consumption of current CMOS technology is already a great challenge. International Technology Roadmap for Semiconductors projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for CMOS circuits in nanoscale technology. We propose a novel ultra-low leakage CMOS circuit structure which we call "sleepy stack". Unlike many other previous approaches, sleepy stack can retain logic state during sleep mode while achieving ultra-low leakage power consumption. We apply the sleepy stack to generic logic circuits. Although the sleepy stack incurs some delay and area overhead, the sleepy stack technique achieves the lowest leakage power consumption among known state-saving leakage reduction techniques, thus, providing circuit designers with new choices to handle the leakage power problem

132 citations

Proceedings ArticleDOI
30 Nov 2008
TL;DR: This work co-designs the control law and the task scheduling algorithm for predictable performance and power consumption for both the computing and the physical systems.
Abstract: The wide applications of cyber-physical systems (CPS) call for effective design strategies that optimize the performance of both computing units and physical plants.We study the task scheduling problem for a class of CPS whose behaviors are regulated by feedback control laws. We co-design the control law and the task scheduling algorithm for predictable performance and power consumption for both the computing and the physical systems. We use a typical example, multiple inverted pendulums controlled by one processor, to illustrate our method.

128 citations

01 Jan 2003
TL;DR: This paper presents a configurable hardware scheduler architecture which minimizes the processor time wasted by the scheduler and time-tick processing.
Abstract: Many real-time applications require a high-resolution time tick in order to work properly. However, supporting a high-resolution time tick imposes a very high overhead on the system. In addition, such systems may need to change scheduling discipline from time to time to satisfy some user requirements such as Quality of Service (QoS). The dynamic changing of the scheduling discipline is usually associated with delays during which some deadlines might be missed. In this paper, we present a configurable hardware scheduler architecture which minimizes the processor time wasted by the scheduler and time-tick processing. The hardware scheduler is flexible and provides three scheduling disciplines: priority-based, rate monotonic and earliest deadline first. The scheduler in hardware also provides accurate timing. The scheduling mode can be changed at runtime, providing support for a wide range of applications on the same device. The hardware scheduler is provided in the form of an Intellectual Property (IP) block that can be customized according to the designer’s input, to suite a certain application, by a tool we have developed.

112 citations

Patent
17 Oct 2002
TL;DR: In this paper, the target system stores a table with global variables and addresses and a module table with system-wide functions and addresses, and a debugger module provides the table with a local name and address of a variable local to the debugger module.
Abstract: Configuration of a debugger that saves resources and debugs on a target system rather than from a host system The target system stores a table with global variables and addresses, and a module table with system-wide functions and addresses In response to a trigger, a debugger module is loaded from the host system and linked to the target system by causing the debugger module to exchange information with the tables The debugger module uses the table to find a variable address and sets a pointer to the address The debugger module provides the table with a local name and address of a variable local to the debugger module The debugger module uses the module table to find an MT address of a function and sets a pointer to the MT address The debugger module provides the module table with an MT address of a function local to the debugger module

99 citations


Cited by
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01 Mar 1999

3,234 citations

Journal ArticleDOI
TL;DR: Barwise and Perry as discussed by the authors tackle the slippery subject of ''meaning, '' a subject that has long vexed linguists, language philosophers, and logicians, and they tackle it in this book.
Abstract: In this provocative book, Barwise and Perry tackle the slippery subject of \"meaning, \" a subject that has long vexed linguists, language philosophers, and logicians.

1,834 citations

Journal ArticleDOI

1,589 citations

Journal ArticleDOI
08 Nov 2004
TL;DR: The paper explores various physical layer research challenges in MIMO-OFDM system design, including physical channel measurements and modeling, analog beam forming techniques using adaptive antenna arrays, and signal processing algorithms used to perform time and frequency synchronization, channel estimation, and channel tracking in M IMO- OFDM systems.
Abstract: Orthogonal frequency division multiplexing (OFDM) is a popular method for high data rate wireless transmission. OFDM may be combined with antenna arrays at the transmitter and receiver to increase the diversity gain and/or to enhance the system capacity on time-varying and frequency-selective channels, resulting in a multiple-input multiple-output (MIMO) configuration. The paper explores various physical layer research challenges in MIMO-OFDM system design, including physical channel measurements and modeling, analog beam forming techniques using adaptive antenna arrays, space-time techniques for MIMO-OFDM, error control coding techniques, OFDM preamble and packet design, and signal processing algorithms used to perform time and frequency synchronization, channel estimation, and channel tracking in MIMO-OFDM systems. Finally, the paper considers a software radio implementation of MIMO-OFDM.

1,475 citations