Vincenzo Rana

Bio: Vincenzo Rana is an academic researcher from Polytechnic University of Milan. The author has contributed to research in topics: Control reconfiguration & Reconfigurable computing. The author has an hindex of 15, co-authored 68 publications receiving 714 citations. Previous affiliations of Vincenzo Rana include École Normale Supérieure & École Polytechnique Fédérale de Lausanne.

BlueSentinel: a first approach using iBeacon for an energy efficient occupancy detection system

Abstract: In the last years, the concept of smart buildings has been proposed and proved to be an effective solution to tackle the problem of reducing the power consumption of complex (both residential and commercial) buildings, while providing the users with a very high level of comfort. In this context, knowing the exact position of users inside the buildings has been identified as a needed feature to optimize the behavior of the building itself. Recently, using the occupants mobile devices as sensors has been validated as an effective solution to have accurate occupancy detection systems, even if no energy efficient solution in therm of battery consumption has been found so far. On the contrary, with this work, we present BLUE-SENTINEL, an accurate and power efficient method to identify the occupants of each room of a smart building using mobile devices as source of information. The proposed approach faces the occupancy detection problem with a good accuracy by exploiting iBeacon, a very recent low-power technology proposed by Apple. In particular, since the iBeacon protocol is built upon Bluetooth Low Energy (BLE), it represents a very highly power-efficient solution. In addition to this, the iBeacon technology is characterized by a good level of compatibility and portability, supporting both iOS- and Android-based devices. The proposed approach has been validated in a real environment with a prototype system released as open source showing how this technology is suitable for the occupancy detection in a smart building.

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

Abstract: Nowadays, multi-core systems-on-chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platforms is growing, as they increase the ability of the initial design to adapt to future modifications. This paper presents a design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC. The proposed methodology is tailored for a reconfigurable hardware architecture based on a flexible communication infrastructure, and exploits applications similarities to obtain an effective mapping. We also introduce a run-time mapper that is able to introduce new applications that were not known at design-time, preserving the mapping of the original system. We apply our design flow to a real-world multimedia case study and to a set of synthetic benchmarks, showing that it is actually able to extract similarities among the applications, as it achieves an average improvement of 29% in terms of reconfiguration latency with respect to a communication-oriented approach, while preserving the same communication performance.

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux

Abstract: Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a multi-FPGA clustered architecture (MFCA). All FPGAs can be partially and dynamically reconfigured to integrate user-defined IP-cores into the system at run-time. For the resource management and communication management we have implemented a Linux operating system on the embedded processor that can be used to control the reconfiguration of the FPGAs by means of simple function calls. Furthermore, the Linux OS completely hides the physical infrastructure of the MFCA from user applications, offering a consistent interface to utilize partial reconfiguration.

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Abstract: Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications. In this context, methods that can lead to versatility enhancements of initial NoC designs to changing working conditions, imposed by variable sets of executed real-life applications at each moment in time, are very important for designing competitive NoCs in industrial SoCs.

Dynamic Reconfigurability in Embedded System Design

Abstract: Nowadays, dynamic reconfigurable embedded systems are widely used, since they have the capability to modify their functionalities, adding or removing components and modify interconnections among them. The basic idea behind these systems is to have the system autonomously modify its functionalities according to the application's changes. This paper describes the area of reconfigurable embedded systems presenting both architectural and methodological aspects trying to point out common features and needs. After a brief introduction, an overview of the models of the reconfigurable architectures, and of the design methodologies was presented.

The knowledge complexity of interactive proof-systems

Abstract: Usually, a proof of a theorem contains more knowledge than the mere fact that the theorem is true. For instance, to prove that a graph is Hamiltonian it suffices to exhibit a Hamiltonian tour in it; however, this seems to contain more knowledge than the single bit Hamiltonian/non-Hamiltonian.In this paper a computational complexity theory of the “knowledge” contained in a proof is developed. Zero-knowledge proofs are defined as those proofs that convey no additional knowledge other than the correctness of the proposition in question. Examples of zero-knowledge proof systems are given for the languages of quadratic residuosity and 'quadratic nonresiduosity. These are the first examples of zero-knowledge proofs for languages not known to be efficiently recognizable.

Highly accurate optic flow computation with theoretically justified warping

Abstract: In this paper, we suggest a variational model for optic flow computation based on non-linearised and higher order constancy assumptions. Besides the common grey value constancy assumption, also gradient constancy, as well as the constancy of the Hessian and the Laplacian are proposed. Since the model strictly refrains from a linearisation of these assumptions, it is also capable to deal with large displacements. For the minimisation of the rather complex energy functional, we present an efficient numerical scheme employing two nested fixed point iterations. Following a coarse-to-fine strategy it turns out that there is a theoretical foundation of so-called warping techniques hitherto justified only on an experimental basis. Since our algorithm consists of the integration of various concepts, ranging from different constancy assumptions to numerical implementation issues, a detailed account of the effect of each of these concepts is included in the experimental section. The superior performance of the proposed method shows up by significantly smaller estimation errors when compared to previous techniques. Further experiments also confirm excellent robustness under noise and insensitivity to parameter variations.

MachSuite: Benchmarks for accelerator design and customized architectures

Abstract: Recent high-level synthesis and accelerator-related architecture papers show a great disparity in workload selection. To improve standardization within the accelerator research community, we present MachSuite, a collection of 19 benchmarks for evaluating high-level synthesis tools and accelerator-centric architectures. MachSuite spans a broad application space, captures a variety of different program behaviors, and provides implementations tailored towards the needs of accelerator designers and researchers, including support for high-level synthesis. We illustrate these aspects by characterizing each benchmark along five different dimensions, highlighting trends and salient features.