Reversible Logic is an emerging field of research which finds its applications in low power computing, Nanotechnology and Quantum Computing. Reversible circuits should have one to one mapping i.e. one input can have only one output so that input vectors can be realized using output vectors. Reversible Circuits require Ancilla(constant inputs) and Garbage Outputs to retain reversibility. An efficient Reversible Circuit can be designed by optimizing their performance parameters. In this paper a \(4 \times 4\) Melior Quantum Multiplier has been proposed which consists of an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs. This proposed multiplier shows an improvement of 21.73% and 18.18% reduction of Ancilla and Garbage Outputs respectively. This multiplier has been implemented in Cadence Virtuoso with average power dissipation of 106.79 nW at 45 nm technology node and used in the implementation of a Linear Phase FIR filter with an average power dissipation of 456.1 nW.

Ultra Power Efficient Melior Quantum Multiplier with Reduced Ancilla and Garbage Outputs

Reversible logic is an emerging technology that is helpful in diverse fields such as genetic programming, high-speed VLSI design, DNA computing and bioinformatics, quantum computing, etc. Reversible computation differs from conventional computation as it safeguards information while manipulating it. Multiplier is a crucial component of Digital Signal Processing (DSP). In general, DSP application requires low power dissipation multiplier. But in conventional computation, the multiplier dissipates more power than a reversible multiplier. In this paper, PERAM deals with reversible array multiplier. As it consists of rudimentary reversible gates like CCNOT and CNOT, analysis will be uncomplicated. The proposed design methodology is implemented and verified in cadence© virtuoso of 45 nm technology showing the improvement of 77.76% in terms of power, 71.39% in terms of power delay product. PERAM shows a great variation in the power and power delay product.

PERAM: Ultra Power Efficient Array Multiplier Using Reversible Logic for High-Performance MAC

Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the multiplication is an important operation in computing systems, some novel reversible multiplier designs are proposed with the parity-preserving property which will be useful for error detection. At first, two optimal signed serial multipliers are presented based on the Booth’s algorithm and its enhanced version called the K-algorithm, utilizing the new arrangements of reversible gates. Then, another low-cost serial multiplier is proposed based on the conventional Add & Shift method to be utilized in the applications in which unsigned numbers are used. Finally, a new signed parallel multiplier is proposed based on the Baugh-Wooley method that is useful for speed-critical applications. The comparative results showed that the proposed multipliers are much better than the existing designs regarding the main criterions used in reversible logic circuits including quantum cost, gate count, constant inputs, and garbage outputs.

https://www.ije.ir/article_85655_e167a6a04383cd556b2d31ea335ce698.pdf

Reversible Logic Multipliers: Novel Low-Cost Parity-Preserving Designs

Any signal processing architecture has a multiplier as its pillar. Its computational capabilities depend on the multiplier's performance. Also, low-power designs are the need of next generation processors. Reversible logic is one of the promising future low power technologies. High-speed multiplication can be achieved if the carry-propagation is faster. Digital compressors have less latency in carry-propagation. In this work, we have explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation. The proposed reversible multiplier is garbage free design and also optimized in terms of delay and quantum cost with the trade-off in ancillary inputs. The proposed multiplier finds its applications in the design of high-speed, low-power signal processing architectures such as convolution, filtering blocks, FFTs and IFTs.

Vinod Kumar Agrawal

Papers

Design of garbage free reversible multiplier for low power applications