Vishnu Kumar Kaliappan

Bio: Vishnu Kumar Kaliappan is an academic researcher from Konkuk University. The author has contributed to research in topics: Model checking & Unified Modeling Language. The author has an hindex of 2, co-authored 3 publications receiving 15 citations.

Designing and Verifying Communication Protocols Using Model Driven Architecture and Spin Model Checker

Abstract: The need of communication protocols in todaypsilas environment increases as much as the network explores. Many new kinds of protocols, e.g. for information sharing, security, etc., are being developed day-to-day which often leads to rapid, premature developments. Many protocols have not scaled to satisfy important properties like deadlock and livelock freedom, since MDA focuses on the rapid development rather than on the quality of the developed models. In order to fix the above, we introduce a 2-Phase strategy based on the UML state machine and sequence diagram to satisfy the properties of communication protocols. We convert these models into PROMELA code for execution on the SPIN model checker. The results are compared with the developed UML models.

Deriving the behavioral properties from UML designs as LTL for model checking

Abstract: Design models help the system development to analyze and visualize its working scenario as a blueprint or a prototype. A successful or error free design leads to an efficient implementation. Thus ensuring the design correctness is a crucial factor in a complex system development like communication protocols. They are reactive in nature and the general verification like correctness evaluation will not yield an effective design because they change their behaviors from time-to-time. One of the way to overcome this problem is to verify their functional behaviors based on the time interval i.e., temporal ordering. To achieve this, an approach called verification property generator is proposed in this paper. The possible functional behaviors are captured in linear temporal logic for the given unified modeling language diagram based on the assumption rules. Here, the safety and liveness properties are defined independently that reduces the verification overhead. The approach is presented in general and hence the properties can be evaluated under any model checking environment.

An approach to verify component-based designs

Abstract: Ensuring design correctness is an important task in the software development and in particular component-based protocol development. We developed a component-oriented design approach for the design of communication protocols and distributed systems. The approach aims at the reuse of components represented by Unified Modeling Language (UML) diagrams. In this paper we propose a verification approach to verify our component-based protocol designs by combing trace equivalence and model checking. Foremost, the internal and external component behaviors are verified independently regarding their formal correctness. Next, the correctness and consistency of compositions are verified. This is achieved by generating the component adaptation path as traces during the composition. The requirements, i.e., safety and liveness properties, are formulated using linear temporal logic formulae. We apply the Spin tool as our model checking mechanism. For this, we present a method for automatically transforming the protocol design components into PROMELA.

A formal verification framework for SysML activity diagrams

Abstract: SysML activity diagrams are OMG/INCOSE standard diagrams used for modeling and specifying probabilistic systems. They support systems composition by call behavior and send/receive artifacts. For verification, the existing approaches dedicated to these diagrams are limited to a restricted set of artifacts. In this paper, we propose a formal verification framework for these diagrams that supports the most important artifacts. It is based on mapping a composition of SysML activity diagrams to the input language of the probabilistic symbolic model checker called ''PRISM''. To prove the soundness of our mapping approach, we capture the underlying semantics of both the SysML activity diagrams and their generated PRISM code. We found that the probabilistic equivalence relation between both semantics preserve the satisfaction of the system requirements. Finally, we demonstrate the effectiveness of our approach by presenting real case studies.

A quantitative verification framework of SysML activity diagrams under time constraints

Abstract: Formal verification framework for probabilistic systems is proposed.SysML activity diagrams is used for system modeling.Automatic transformation of activity diagram into PRISM language.The soundness of the proposed framework is proved. Time-constrained and probabilistic verification approaches gain a great importance in system behavior validation including avionic, transport risk assessment, automotive systems and industrial process controllers. They enable the evaluation of system behavior according to the design requirements and ensure their correctness before any implementation. Due to the difficulty of analyzing, modeling and verifying these large scale systems, we introduce a novel verification framework based on PRISM probabilistic model checker that takes the SysML activity diagram as input and produce their equivalent timed probabilistic automata that is/are expressed in PRISM language. To check the functional correctness of the system under test, the properties are expressed in PCTL temporal logic. To prove the soundness of our mapping approach, we capture the underlying semantics of both the SysML activity diagrams and their generated PRISM code. We found that the timed probabilistic equivalence relation between both semantics preserve the satisfaction of the system requirements. We present digital camera as case study to illustrate the applicability of the proposed approach and to demonstrate its efficiency by analyzing a performability properties.

Synthesizing Distributed Protocol Specifications from a UML State Machine Modeled Service Specification

Abstract: The object-oriented paradigm is widely applied in designing and implementing communication systems. Unified Modeling Language (UML) is a standard language used to model the design of object-oriented systems. A protocol state machine is a UML adopted diagram that is widely used in designing communication protocols. It has two key attractive advantages over traditional finite state machines: modeling concurrency and modeling nested hierarchical states. In a distributed communication system, each entity of the system has its own protocol that defines when and how the entity exchanges messages with other communicating entities in the system. The order of the exchanged messages must conform to the overall service specifications of the system. In object-oriented systems, both the service and the protocol specifications are modeled in UML protocol state machines. Protocol specification synthesis methods have to be applied to automatically derive the protocol specification from the service specification. Otherwise, a time-consuming process of design, analysis, and error detection and correction has to be applied iteratively until the design of the protocol becomes error-free and consistent with the service specification. Several synthesis methods are proposed in the literature for models other than UML protocol state machines, and therefore, because of the unique features of the protocol state machines, these methods are inapplicable to services modeled in UML protocol state machines. In this paper, we propose a synthesis method that automatically synthesizes the protocol specification of distributed protocol entities from the service specification, given that both types of specifications are modeled in UML protocol state machines. Our method is based on the latest UML version (UML2.3), and it is proven to synthesize protocol specifications that are syntactically and semantically correct. As an example application, the synthesis method is used to derive the protocol specification of the H.323 standard used in Internet calls.

A probabilistic and timed verification approach of SysML state machine diagram

Abstract: Timed-constrained and probabilistic verification approaches gain a great importance in system behavior validation. They enable the evaluation of system behavior according to the design requirements and ensure their correctness before any implementation. In this paper, we propose a probabilistic and timed verification framework of State Machine diagrams extended with time and probability features. The approach consists on mapping the extended State Machine diagram to its equivalent probabilistic timed automata that is expressed in PRISM language. To check the functional correctness of the system under test, the properties are expressed in PCTL temporal logic. We demonstrate the approach efficiency by analyzing performability properties on a Automatic Teller Machine (ATM) case study.