Vivek Sharma

Bio: Vivek Sharma is an academic researcher from National Institute of Technology Goa. The author has contributed to research in topics: CMOS & Operational amplifier. The author has an hindex of 2, co-authored 11 publications receiving 15 citations. Previous affiliations of Vivek Sharma include LNM Institute of Information Technology.

Design of a hybrid ring oscillator at 1.5/3.0 GHz with low power supply sensitivity

Abstract: In this paper a hybrid ring oscillator, with oscillation frequency of 1.5/3.0 GHz, is presented with reduced sensitivity for supply variations. An analysis of oscillation frequency variation due to static and dynamic power supply noise, is given. Simulation results show a static supply sensitivity of 1.06% at 200 mV static supply noise and a dynamic supply sensitivity of 2.54% (worst case) as compared to 16.55% dynamic sensitivity of a conventional ring oscillator at 50 mV(peak-to-peak), 10 MHz sinusoidal noise signal. The design is simulated at 180 nm standard CMOS technology at different stages 3/5/7 having a maximum power consumption of 5.2 mW and supply voltage of 1.8 V.

Two-Step Flash ADC Using Standard Cell Based Flash ADCs

Abstract: In this paper, a 9-bit resolution two-step Flash Analog-to-Digital Converter (ADC) is designed using standard cell based comparators. The standard cell-based comparators are designed with basic gates like NOT, NOR, NAND and their combinations in order to generate the required built-in reference voltage. This replaces the need of conventional dynamic comparators and the resistor ladder. The NMOS and PMOS used in the standard cells are designed using a constant aspect ratio to facilitate the semi-automated synthesis. These comparators consume less area, power and are less sensitive to noise. The ADC is designed in a CMOS 180 nm process with supply voltage of 1.8 V. The architecture operates at a 28.57 MS/s with a power consumption of 7.68 mW. The effective number of bits achieved for the design is 8.41 bits.

A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications

Abstract: This brief presents a low-power tunable $G_{m}-C$ complex filter for wireless receiver applications. The proposed design achieves an unconditional stability thanks to the internal negative feedback mechanism. This negative feedback helps in achieving a high-frequency shift and the negative transconductance of the circuit improves the Image Rejection Ratio (IRR) and Common Mode Rejection Ratio (CMRR) of the proposed design. The proposed circuit has independent control over bandwidth and frequency shift which makes an attractive solution for multi-standard and multi-mode wireless receiver applications. A second order complex filter is designed for Long Term Evolution (LTE) application and used as a test vehicle to verify the proposed concept. The circuit is designed using a 180 nm CMOS process with a power consumption of $106~\mu \text{W}$ from a 1 V supply voltage. It is centered at 9.2 MHz with −3 dB bandwidth of 1.4 MHz and provides an IRR of 51 dB with a voltage gain of 45 dB. The total integrated in-band Input Referred Noise (IRN) is $70~\mu V_{rms}$ and FoM of 47 aJ is achieved. The area of the layout of the proposed design is $78~\mu \text{m}$ X $78~\mu \text{m}$ .

36 μW fourth order sigma-delta modulator using single operational amplifier

Abstract: This paper presents a single loop fourth-order Discrete-Time Sigma-Delta Modulator (ΣΔM) using single Operational Amplifier (Op-Amp). Proposed ΣΔM utilises delay-based discrete-time integrators and...

Microbiological Quality Analysis of the Pastry sold in the Jalandhar City and Public Perception about the Pastry

Abstract: Bakery product Pastry is a commonly consumed food throughout the year. It harbors many potent pathogens, its microbial quality especially bacteriological as well as yeast and mold quality has always been crucially important to public health. This study was aims to access the bacteriological as well as yeast and mold quality of the pastry sold in the different markets in the Jalandhar city. Randomly 40 pastry samples were collected from the different retail shops and studied to determine the colony forming units per gram of the pastry samples. For aerobic colony counts samples were classified as satisfactory, acceptable and unsatisfactory categories according to PHLS (Public Health Laboratory Services, UK) guidelines. For yeast and mold counts, WQAS (Woolworths Quality Assurance Standard) guidelines were followed. In aerobic colony counts, all the samples of the 10 zones selected for the study, showed heavy contamination of bacteria ranging 1.37*106 cfu/g to 11.27*106 cfu/g. Whereas yeast and mold counts ranging 1.33*105cfu/g to 92.5*105cfu/g. Public perception was also taken care about the food. A structured questionnaire was administered to 104 public members in Jalandhar city. Most respondents (78.8%) consumed pastry. Some (28.8%) felt ill from eating pastry, but only (12.5%) reported to a medical doctor/health authority. The paper recommends that there is need to minimize the contamination and HACCP systems could be applied to the control of the spoilage microorganisms at all stages of manufacture, storage, transport and retail steps as well as there is need for health education in order to ensure food safety for the consumers.

ΣΔ Data Converters

Abstract: First written in 2003 for a book that was never published. Last updated on January 29, 2011. You can find the most recent version at www.designers-guide.org. Contact the author via email at monte.mar@comcast.net. Permission to make copies, either paper or electronic, of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage and that the copies are complete and unmodified. To distribute otherwise, to publish, to post on servers, or to distribute to lists, requires prior written permission.

Design an optimal digital phase lock loop with current-starved ring VCO using CMOS technology

Abstract: This paper describes the design of an optimal and low power Digital Phase Lock Loop (DPLL). It consumes the 485 mV power using 45 nm CMOS technology on CADENCE Virtuoso software. DPLL used for fast speed, less noise or jitter and large bandwidth with very fast acquisition time in wireless or wire line communication for modulator or demodulator. Clock recover, clock synchronization are the important factor in which PLL used. In digital system and microprocessor the DPLL uses for the clock generation and frequency synthesizer. DPLL consist the phase detector, low pass filter and VCO. The VCO produced oscillations at 8.5 Ghz. The average power dissipation or power consumption of DPLL is 485mV at an input voltage of 2 V. The results show that of the proposed DPLL design used for less power consumption, high speed operations applications.

A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications

Abstract: This paper presents a low-power second-order continuous-time (CT) Delta-Sigma Modulator (DSM) using a new design methodology for biomedical applications. The proposed design methodology first implements a target block with the highest power consumption at a transistor level before optimizing the DSM coefficients. We are also able to reduce the area usage by appropriate limitations on the DSM range in the proposed design process. The DSM was implemented using the genetic algorithm (GA) and appropriate chopping techniques in our design process. The design was implemented in 0.18um CMOS technology by using a 0.083 mm2 layout, with a maximum SNDR and dynamic range of 94.28 and 100 dB, respectively, for a 2 kHz bandwidth and 32.34uW power consumption.