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Author

Vojin G. Oklobdzija

Other affiliations: IBM, University of California, University of Sydney  ...read more
Bio: Vojin G. Oklobdzija is an academic researcher from University of Texas at Dallas. The author has contributed to research in topics: Adder & Logic gate. The author has an hindex of 37, co-authored 173 publications receiving 5578 citations. Previous affiliations of Vojin G. Oklobdzija include IBM & University of California.


Papers
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Journal ArticleDOI
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Abstract: In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.

660 citations

Journal ArticleDOI
TL;DR: The design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented and it is found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage.
Abstract: Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.

436 citations

Journal ArticleDOI
TL;DR: The proposed method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known, and it is easy to incorporate this method in silicon compilation or logic synthesis tools.
Abstract: This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1 /spl mu/ CMOS ASIC technology.

370 citations

Journal ArticleDOI
TL;DR: In this article, a pass-transistor adiabatic logic (PAL) was proposed to operate from a single power-clock supply and outperforms the previously reported adiabilistic logic techniques in terms of its energy use.
Abstract: We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use. PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 /spl mu/ CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage PAL shift register fabricated in the 1.2 /spl mu/ CMOS technology has been experimentally verified.

221 citations

Journal ArticleDOI
TL;DR: CAL is a dual-rail logic that operates from a single-phase AC power-clock supply that makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution.
Abstract: The design and experimental evaluation of a clocked adiabatic logic (GAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution. CAL can also be operated from a DC power supply in a nonenergy-recovery mode compatible with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 /spl mu/m CMOS technology. Experimental results show that energy savings are achieved at clock frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabatic and nonadiabatic modes, power management strategies may be based upon switching between modes when necessary.

182 citations


Cited by
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Book ChapterDOI
15 Aug 1999
TL;DR: In this paper, the authors examine specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. And they also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.
Abstract: Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

6,757 citations

Journal ArticleDOI
TL;DR: The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
Abstract: The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

1,720 citations

Journal ArticleDOI
01 Apr 2011-Science
TL;DR: An inventory of the world’s technological capacity from 1986 to 2007 reveals the evolution from analog to digital technologies, and the majority of the authors' technological memory has been in digital format since the early 2000s.
Abstract: We estimated the world’s technological capacity to store, communicate, and compute information, tracking 60 analog and digital technologies during the period from 1986 to 2007. In 2007, humankind was able to store 2.9 × 10 20 optimally compressed bytes, communicate almost 2 × 10 21 bytes, and carry out 6.4 × 10 18 instructions per second on general-purpose computers. General-purpose computing capacity grew at an annual rate of 58%. The world’s capacity for bidirectional telecommunication grew at 28% per year, closely followed by the increase in globally stored information (23%). Humankind’s capacity for unidirectional information diffusion through broadcasting channels has experienced comparatively modest annual growth (6%). Telecommunication has been dominated by digital technologies since 1990 (99.9% in digital format in 2007), and the majority of our technological memory has been in digital format since the early 2000s (94% digital in 2007).

1,450 citations

Book
24 Jun 2003
TL;DR: Digital Arithmetic, two of the field's leading experts, deliver a unified treatment of digital arithmetic, tying underlying theory to design practice in a technology-independent manner, to develop sound solutions, avoid known mistakes, and repeat successful design decisions.
Abstract: Digital arithmetic plays an important role in the design of general-purpose digital processors and of embedded systems for signal processing, graphics, and communications. In spite of a mature body of knowledge in digital arithmetic, each new generation of processors or digital systems creates new arithmetic design problems. Designers, researchers, and graduate students will find solid solutions to these problems in this comprehensive, state-of-the-art exposition of digital arithmetic. Ercegovac and Lang, two of the field's leading experts, deliver a unified treatment of digital arithmetic, tying underlying theory to design practice in a technology-independent manner. They consistently use an algorithmic approach in defining arithmetic operations, illustrate concepts with examples of designs at the logic level, and discuss cost/performance characteristics throughout. Students and practicing designers alike will find Digital Arithmetic a definitive reference and a consistent teaching tool for developing a deep understanding of the "arithmetic style" of algorithms and designs. Guides readers to develop sound solutions, avoid known mistakes, and repeat successful design decisions. Presents comprehensive coveragefrom fundamental theories to current research trends. Written in a clear and engaging style by two masters of the field. Concludes each chapter with in-depth discussions of the key literature. Includes a full set of over 250 exercises, an on-line appendix with solutions to one-third of the exercises and 600 lecture slides

742 citations

Proceedings Article
01 Jan 2002
TL;DR: A set of logic gates and flip-flops needed for cryptographic functions and compared those to Static Complementary CMOS implementations to protect security devices such as smart cards against power attacks are built.
Abstract: To protect security devices such as smart cards against power attacks, we propose a dynamic and differential CMOS logic style. The logic operates with a power consumption independent of both the logic values and the sequence of the data. Consequently, it will not reveal the sensitive data in a device. We have built a set of logic gates and flip-flops needed for cryptographic functions and compared those to Static Complementary CMOS implementations.

589 citations