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Vugranam C. Sreedhar

Researcher at IBM

Publications -  73
Citations -  3092

Vugranam C. Sreedhar is an academic researcher from IBM. The author has contributed to research in topics: Component (UML) & Set (abstract data type). The author has an hindex of 26, co-authored 73 publications receiving 3062 citations. Previous affiliations of Vugranam C. Sreedhar include Hewlett-Packard & McGill University.

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The Jalapeño virtual machine

TL;DR: Jalapeno is a virtual machine for JavaTM servers written in the Java language to be as self-sufficient as possible and to obtain high quality code for methods that are observed to be frequently executed or computationally intensive.
Proceedings ArticleDOI

Escape analysis for Java

TL;DR: A new program abstraction for escape analysis, the connection graph, that is used to establish reachability relationships between objects and object references is introduced and it is shown that the connectiongraph can be summarized for each method such that the same summary information may be used effectively in different calling contexts.
Proceedings ArticleDOI

The Jalapeño dynamic optimizing compiler for Java

TL;DR: The optimal order for basic block generation that minimizes number of regeneration is a topological order (ignoring the back edges), however, because BC2IR computes the control ow graph in the same pass, it cannot compute the optimal order a priori.
Journal ArticleDOI

Stack allocation and synchronization optimizations for Java using escape analysis

TL;DR: An escape analysis framework for Java is presented to determine (1) if an object is not reachable after its method of creation returns, allowing the object to be allocated on the stack, and (2) if a object is reachable only from a single thread during its lifetime, allowing unnecessary synchronization operations on that object to been removed.
Proceedings ArticleDOI

Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures

TL;DR: The Synchronization State Buffer is proposed, a scalable architectural design for fine-grain synchronization that efficiently performs synchronizations between concurrent threads that records and manages the states of frequently synchronized data using modest hardware support.