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W.A.H. Wien

Bio: W.A.H. Wien is an academic researcher. The author has contributed to research in topics: Deep reactive-ion etching & Reactive-ion etching. The author has an hindex of 1, co-authored 1 publications receiving 40 citations.

Papers
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TL;DR: In this paper, a silicon micromachining method, which combines tetra methyl ammonium hydroxide (TMAH) etching and deep-reactive ion etching (DRIE) along with bottom-up copper electroplating, is presented to fabricate high-density and high-aspect ratio through-wafer electrical interconnects (TWEIs) for three-dimensional multichip packaging.
Abstract: This paper presents a novel silicon micromachining method, which combines tetra methyl ammonium hydroxide (TMAH) etching and deep-reactive ion etching (DRIE) along with bottom-up copper electroplating, to fabricate high-density and high-aspect ratio through-wafer electrical interconnects (TWEIs) for three-dimensional multichip packaging. The silicon wafer was locally etched with TMAH from the backside until the desired membrane thickness was reached, and then DRIE was performed on the membrane until the holes were etched through. TMAH etching preserved large areas of the wafers at the original thickness, thus, ensuring relatively strong mechanical strength and manipulability. DRIE made it possible to realize high-aspect ratio holes with minimized wafer area consumption. A new bottom-up copper electroplating technique was developed to fill the high-aspect ratio through-wafer holes. This method can avoid seams and voids while achieving attractive electrical features. Through-wafer holes, as small as 5 mum in diameter, have been realized by using the combination of TMAH and DRIE, and have been completely and uniformly filled by using bottom-up copper electroplating

41 citations


Cited by
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Journal ArticleDOI
Zheyao Wang1
TL;DR: The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics as discussed by the authors.
Abstract: After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore’s Law without needing to continuously shrink feature sizes The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics This 3-D hetero-integration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications This paper reviews the following aspects of the MEMS/microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/microsensor products using 3-D integration technologies Of particular interest throughout this paper is the hetero-integration of the MEMS and CMOS technologies [2015-0158]

94 citations

Journal ArticleDOI
TL;DR: In this article, the fabrication of void-free copper-filled through-glass-vias (TGVs) and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme is presented.
Abstract: We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test.

69 citations

Journal ArticleDOI
Chongshen Song1, Zheyao Wang1, Qianwen Chen1, Jian Cai1, Litian Liu1 
TL;DR: Wang et al. as mentioned in this paper proposed a bottom-up copper electroplating technique to fill high aspect ratio vias with copper, which can offer significant improvements over planar integrated circuits (ICs) on performance, functionality, and integration density.

60 citations

Journal ArticleDOI
TL;DR: To demonstrate the effectiveness of the C-TSV structure for wafer-level 3D integration, feasibility study of the implementation of the novel process and mechanics comparisons of these two 3D chip stacking structures under thermal loading through finite element (FE) stress simulation are made.

57 citations

Journal ArticleDOI
Zheyao Wang1
TL;DR: The fundamental fabrication technologies of 3D integration are introduced, the recent progresses of MEMS and microsystems using 3D Integration and TSV technologies are reviewed, and the conclusions are made and the future trends are discussed.

45 citations