W.A.M. Van Noije

Bio: W.A.M. Van Noije is an academic researcher from University of São Paulo. The author has contributed to research in topics: CMOS & Dual-modulus prescaler. The author has an hindex of 11, co-authored 31 publications receiving 443 citations. Previous affiliations of W.A.M. Van Noije include Katholieke Universiteit Leuven.

A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)

Abstract: The implementation of a dual-modulus prescaler (divide by 128/129) using an extension of the true-single-phase-clock (TSPC) technique, the extended TSPC (E-TSPC), is presented. The E-TSPC consists of a set of composition rules for single-phase-clock circuits employing static, dynamic, latch, data-precharged, and NMOS-like CMOS blocks. The composition rules, as well as the CMOS blocks, are described and discussed. The experimental results of the complete dual-modulus prescaler, implemented in a 0.8 /spl mu/m CMOS process, show a maximum 1.59 GHz operation rate at 5 V with 12.8 mW power consumption. They are compared with the results from other recent implementations showing that the proposed E-TSPC circuit can reach high speed with both smaller area and lower power consumption.

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution

Abstract: This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 /spl mu/m CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution. >

SAMPA Chip : The New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

Abstract: This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

Advanced CMOS gate array architecture combining `gate isolation' and programmable routing channels

Abstract: A description is given of a novel CMOS gate array architecture for LSI/VLSI complexity The new structure is based on the `gate isolation' technique for logic implementation, in addition to the programmability of the amount of routing channels This concept uses double-level metal with the first contact level programmable for the circuit customization The gate array has been designed in a 3-/spl mu/m Si-gate CMOS process A maximum 2-input gate density of 290 gates/mm/SUP 2/ can be achieved As a test vehicle for this novel gate array structure, a ninth-order LDI digital filter (4652 transistors) has been designed automatically with the aid of the gate array design system (GARDS) layout tool, on a 3/spl times/3 mm/SUP 2/ gate array size In a first approach, the filter has been realized with the internal gate structure as used in classical gate arrays, and in a second approach the same filter has been laid out on 60% of the array size using the new concept In this last version as much as 40% reduction of silicon area has been achieved

A methodology for CMOS low noise amplifier design

Abstract: An intuitive strategy for CMOS low noise amplifier (LNA) design, compromising noise and linearity performance optimization, is presented. Analytical expressions for noise factor and IM3 are derived. The gain and power dissipation are considered pre-fixed parameters for this approach. A 2.4 GHz LNA has been designed and simulated in a 0.35 /spl mu/m CMOS technology to validate the proposed methodology.

Photonic crystals

Abstract: The term photonic crystals appears because of the analogy between electron waves in crystals and the light waves in artificial periodic dielectric structures. During the recent years the investigation of one-, two-and three-dimensional periodic structures has attracted a widespread attention of the world optics community because of great potentiality of such structures in advanced applied optical fields. The interest in periodic structures has been stimulated by the fast development of semiconductor technology that now allows the fabrication of artificial structures, whose period is comparable with the wavelength of light in the visible and infrared ranges.

A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line

Abstract: This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-/spl mu/m digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding /spl plusmn/1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

Abstract: This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology

Abstract: A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

Abstract: A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.