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W.D. Pan

Bio: W.D. Pan is an academic researcher from University of Alabama. The author has contributed to research in topics: Motion estimation & Quarter-pixel motion. The author has an hindex of 10, co-authored 25 publications receiving 382 citations. Previous affiliations of W.D. Pan include University of Louisiana at Lafayette & University of Alabama in Huntsville.

Papers
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Journal Article
TL;DR: The inputs and outputs of reversible logic gates can be uniquely retrievable from each other, which makes them very attractive for applications where extremely low power consumption, or heat dissipation, is desirable.
Abstract: This work presents the logical reversibility. The inputs and outputs of reversible logic gates can be uniquely retrievable from each other. The reversible logic operations can't erase information and dissipate zero heat. The circuit actually operates in a backward operation, allows reproducing the inputs from the outputs and consumes zero power. As the basic elements of any logic circuit, logic gates are used to realize Boolean functions. By combining reversible logic gates, reversible circuits can perform complex logical and arithmetic operations. A one-to-one mapping between inputs and outputs is realized. The logical operations run backwards by cascading a reversible logic gate with its dual (inverse). Reversible circuits are also called lossless circuits, as there is neither energy loss nor information loss. These circuits are very attractive for applications where extremely low power consumption, or heat dissipation, is desirable in areas ranging from communications, low power VLSI (very large-scale integration) technology, optical computing to nanotechnology. Reversible logic found to be very useful in quantum computing where the quantum evolution is inherently reversible.

118 citations

Journal ArticleDOI
TL;DR: Finite word-length simulations demonstrate the viability and excellent performance of NEDA, a new DA architecture aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in digital signal processing (DSP) applications.
Abstract: Conventional distributed arithmetic (DA) is popular in application-specific integrated circuit (ASIC) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed, aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in digital signal processing (DSP) applications. Mathematical analysis proves that DA can implement inner product of vectors in the form of two's complement numbers using only additions, followed by a small number of shifts at the final stage. Comparative studies show that NEDA outperforms widely used approaches such as multiply/accumulate (MAC) and DA in many aspects. Being a high-speed architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. A hardware compression scheme is introduced to generate a butterfly structure with minimum number of additions. NEDA-based architectures for 8 /spl times/ 8 discrete cosine transform (DCT) core are presented as an example. Savings exceeding 88% are achieved, when the compression scheme is applied along with NEDA. Finite word-length simulations demonstrate the viability and excellent performance of NEDA.

76 citations

Proceedings ArticleDOI
25 Apr 2002
TL;DR: A new distributed arithmetic architecture, NEDA, is presented in this paper, a low power optimized architecture based on the distributed arithmetic paradigm that offers high speed and reduced area.
Abstract: A new distributed arithmetic architecture, NEDA, is presented in this paper. NEDA is a low power optimized architecture based on the distributed arithmetic paradigm. In addition to low power performance, NEDA offers high speed and reduced area. In NEDA, inner product computational module has been proved, mathematically, to require only additions. Moreover, minimum number of additions is used by exploiting the redundancy in the adder array. Such properties have made a NEDA unit a basic computational module for high performance DSP architectures. A case study of 8/spl times/8 DCT NEDA-based architecture is analyzed. Savings exceeding 88% are achieved for the DCT implementation.

33 citations

Journal ArticleDOI
TL;DR: The current status of quantum computers, quantum computer systems, and quantum simulators is surveyed and Shor's algorithm is briefly surveyed, which performs factoring a large integer in polynomial time while classical factoring algorithms can do it in exponential time.
Abstract: Quantum computing is an emerging technology. The clock frequency of current computer processor systems may reach about 40 GHz within the next 10 years. By then, one atom may represent one bit. Electrons under such conditions are no longer described by classical physics and a new model of the computer may be necessary by then. The quantum computer is one proposal that may have merit in dealing with the problems associated with the fact that certain important computationally intense problems present that current (classical) computers cannot solve because they require too much processing time. For example, Shor's algorithm performs factoring a large integer in polynomial time while classical factoring algorithms can do it in exponential time. In this paper we briefly survey the current status of quantum computers, quantum computer systems, and quantum simulators. Keywords Classical computers, quantum computers, quantum computer systems, quantum simulators, Shor's algorithm.

27 citations

Proceedings ArticleDOI
12 Nov 2007
TL;DR: This paper proposes to select only a small subset of the pixels in estimating the global motion parameters, based on a combination of fixed and random subsampling patterns, which were found to provide better motion estimation accuracy/complexity tradeoffs than those achievable by using either fixed or random patterns alone.
Abstract: Global motion generally describes the motion of the camera, although it may comprise large object motion. The region of support for global motion representation consists of the entire image frame. Therefore, estimating global motion parameters tends to be computationally costly due to the involvement of all the pixels in the calculation. Efficient global motion estimation (GME) techniques are sought after in many applications such as video coding, image stabilization and super-resolution. In this paper, we propose to select only a small subset of the pixels in estimating the global motion parameters, based on a combination of fixed and random subsampling patterns. Simulation results demonstrate that the proposed method was able to speed up the conventional all-pixel GME approach by up to 7 times, without significant loss in the estimation accuracy. The combined subsampling patterns were also found to provide better motion estimation accuracy/complexity tradeoffs than those achievable by using either fixed or random patterns alone.

24 citations


Cited by
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Journal ArticleDOI
TL;DR: This paper provides an overview of the fundamentals of natural computing, particularly the fields listed above, emphasizing the biological motivation, some design principles, their scope of applications, current research trends and open problems.

278 citations

Journal ArticleDOI
TL;DR: In this article, a blind watermarking algorithm in DCT domain using the correlation between two DCT coefficients of adjacent blocks in the same position is presented. But the proposed algorithm is tested for different attacks and it shows very good robustness under JPEG image compression as compared to existing one.
Abstract: This paper presents a novel blind watermarking algorithm in DCT domain using the correlation between two DCT coefficients of adjacent blocks in the same position. One DCT coefficient of each block is modified to bring the difference from the adjacent block coefficient in a specified range. The value used to modify the coefficient is obtained by finding difference between DC and median of a few low frequency AC coefficients and the result is normalized by DC coefficient. The proposed watermarking algorithm is tested for different attacks. It shows very good robustness under JPEG image compression as compared to existing one and also good quality of watermark is extracted by performing other common image processing operations like cropping, rotation, brightening, sharpening, contrast enhancement etc.

206 citations

Journal ArticleDOI
TL;DR: It is shown that the proposed reversible BCD adder has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and garbage outputs with compared to the existing counterparts.
Abstract: This paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as "Copying Circuit" to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all Boolean functions. It also can be used to design optimized adder architectures. This paper also proposes a novel reversible full adder. One of the prominent functionalities of the proposed HNG gate is that it can work singly as a reversible full adder unit. The proposed reversible full adder contains only one gate. We show that its hardware complexity is less than the existing reversible full adders. The proposed full adder is then applied to the design of a reversible 4-bit parallel adder. A reversible Binary Coded Decimal (BCD) adder circuit is also proposed. The proposed circuit can add two 4-bit binary variables and it transforms the result into the appropriate BCD number using efficient error correction modules. We show that the proposed reversible BCD adder has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and garbage outputs with compared to the existing counterparts.

167 citations

01 Jan 2008
TL;DR: A novel 4x4 bit reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers and can be generalized for NxN bit multiplication.
Abstract: Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterparts. It is also better than the existing counterparts in term of number of gates, garbage outputs and constant inputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "HNG". The reversible HNG gate can work singly as a reversible full adder. In this paper we use HNG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication. We can use it to construct more complex systems in nanotechnology.

151 citations

Journal ArticleDOI
TL;DR: Two new 4 × 4 bit reversible multiplier designs are presented which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers.
Abstract: Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

114 citations