W. Graham

Bio: W. Graham is an academic researcher from IBM. The author has contributed to research in topics: Polyimide & Layer (electronics). The author has an hindex of 11, co-authored 25 publications receiving 953 citations.

High-speed signal propagation on lossy transmission lines

Abstract: This paper addresses some of the problems encountered in propagating high-speed signals on lossy transmission lines encountered in high-performance computers. A technique is described for including frequency-dependent losses, such as skin effect and dielectric dispersion, in transmission line analyses. The disjoint group of available tools is brought together, and their relevance to the propagation of high-speed pulses in digital circuit applications is explained. Guidelines are given for different interconnection technologies to indicate where the onset of severe dispersion takes place. Experimental structures have been built and tested, and this paper reports on their electrical performance and demonstrates the agreement between measured data and waveforms derived from analysis. The paper addresses the problems found on lossy lines, such as reflections, rise-time slowdown, increased delay, attenuation, and crosstalk, and suggests methods for controlling these effects in order to maintain distortion-free propagation of high-speed signals.

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

Abstract: This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

A practical implementation of silicon microchannel coolers for high power chips

Abstract: The paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance of 10.5 C-mm/sup 2//W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of less than 35 kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300 W/cm/sup 2/. Coolers of this design should be able to cool chips with average power densities of 400 W/cm/sup 2/ or more.

Nano/Microwire Solar Cell Fabricated by Nano/Microsphere Lithography

Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof. The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof. A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.

Electroless Deposition of Cu on Glass and Patterning with Microcontact Printing

Abstract: Electroless-depositing a metal from solution to a substrate and patterning it using microcontact printing is an alternative to the conventional patterning of vacuum-deposited metals using photolithography. Here, we pattern Cu onto 15 × 15 sq-inch glass substrates by (i) self-assembly of a thin layer of amino-derivatized silanes to the glass, (ii) binding Pd/Sn catalytic particles to the silanes, (iii) electroless deposition of ∼120 nm of Cu on the catalytic surface, (iv) microcontact printing hexadecanethiol on the Cu film using an accurate printing tool, and (v) selectively etching the printed Cu using hexadecanethiol as a resist. This method is particularly attractive for the fabrication of metallic gates for thin-film transistor liquid-crystal displays.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Thin film transistor, method of manufacturing the same, and flat panel display having the same

Abstract: A thin film transistor (TFT), a method of manufacturing the TFT, and a flat panel display comprising the TFT are provided. The TFT includes a gate, a gate insulating layer that contacts the gate, a channel layer that contacts the gate insulating layer and faces the gate with the gate insulating layer therebetween, a source that contacts an end of the channel layer; and a drain that contacts an other end of the channel layer, wherein the channel layer is an amorphous oxide semiconductor layer, and each of the source and the drain is a conductive oxide layer comprising an oxide semiconductor layer having a conductive impurity in the oxide semiconductor layer. A low resistance metal layer can further be included on the source and drain. A driving circuit of a unit pixel of a flat panel display includes the TFT.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Engineering silicon oxide surfaces using self-assembled monolayers.

Abstract: Although a molecular monolayer is only a few nanometers thick it can completely change the properties of a surface. Molecular monolayers can be readily prepared using the Langmuir-Blodgett methodology or by chemisorption on metal and oxide surfaces. This Review focuses on the use of chemisorbed self-assembled monolayers (SAMs) as a platform for the functionalization of silicon oxide surfaces. The controlled organization of molecules and molecular assemblies on silicon oxide will have a prominent place in bottom-up nanofabrication, which could revolutionize fields such as nanoelectronics and biotechnology in the near future. In recent years, self-assembled monolayers on silicon oxide have reached a high level of sophistication and have been combined with various lithographic patterning methods to develop new nanofabrication protocols and biological arrays. Nanoscale control over surface properties is of paramount importance to advance from 2D patterning to 3D fabrication.

Simulation of high-speed interconnects

Abstract: With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail.