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Author

W.J.M. Philipsen

Other affiliations: Motorola, Magma Design Automation
Bio: W.J.M. Philipsen is an academic researcher from Eindhoven University of Technology. The author has contributed to research in topics: Physical design & Artificial neural network. The author has an hindex of 6, co-authored 10 publications receiving 315 citations. Previous affiliations of W.J.M. Philipsen include Motorola & Magma Design Automation.

Papers
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Patent•
24 Apr 2000
TL;DR: In this article, a common database is used to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions, which can be used to reduce the need to translate circuit descriptions between tools.
Abstract: An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The common database includes entities, models, cells, pins, busses and nets. The data-flow graphs are stored as graphs, the nodes in a graph as cells, and the edges as busses. Physical design data is available by storing the cells in a model in a KD tree. This allows queries on cells in the netlist located in the layout within arbitrary areas.

230 citations

Journal Article•DOI•
TL;DR: Matisse is an architectural design tool that increases productivity without sacrificing area, performance, or power and supports the diverse design practices required for commodity IC design by giving the designer fine-grain control of behavioral synthesis tasks.
Abstract: To accelerate industrial adoption of behavioral synthesis, we have developed Matisse, an architectural design tool that increases productivity without sacrificing area, performance, or power. Matisse's main difference from traditional behavioral synthesis tools is that it lets the designer play a key role. It allows the designer to make major decisions about styles, protocols, parallelism, delays, and partial or even complete architectures before the behavioral synthesis phase starts. Then it enables the designer to incorporate these decisions into the architecture using behavioral synthesis. Matisse supports the diverse design practices required for commodity IC design by giving the designer fine-grain control of behavioral synthesis tasks.

27 citations

Patent•
03 Dec 1996
TL;DR: In this article, a register transfer logic (RTL) implementation of an integrated circuit is generated by performing a set of design tasks, which can be modified by branching to another design task such that the design tasks are performed in any order.
Abstract: A computer implemented architectural design method for designing an integrated circuit. An algorithmic description of the behavior of the integrated circuit is created (step 202), from which a register transfer logic (RTL) implementation (400, 500) of the integrated circuit is generated by performing a set of design tasks (steps 204-212). The RTL implementation is modified after performing one of the design tasks by branching to another design task such that the design tasks are performed in any order. Data is stored in a common database (12) which can be edited interactively through one of a plurality of data editors (14-22).

18 citations

Proceedings Article•DOI•
11 Jun 1991
TL;DR: A novel neural network solution for the graph coloring problem using the combination of the Hopfield type of neurons and the Potts neurons for minimizing the number of colors needed is used.
Abstract: A novel neural network solution is presented for the graph coloring problem. The algorithm is an extension of the algorithm proposed by D.H. Ballard et al. (1987). By adding Potts neurons, it was possible to reduce the search space without excluding feasible solutions. The combination of the Hopfield type of neurons and the Potts neurons for minimizing the number of colors needed is used. The neural network has been programmed in C/sup ++/ and implemented on an Alliant FX-8 computer. The results obtained for a large number of graphs show the effectiveness of the algorithm, and the applicability of the proposed technique to one out of n programming problems. >

15 citations

Proceedings Article•DOI•
11 Jun 1991
TL;DR: In this article, an exact algorithm for module allocation on module allocation graphs that are comparability graphs is presented, which takes into account the first-order effects of the interconnection weights, and a description of the constraints on the library and the schedule for the module allocation graph to be comparability graph is presented.
Abstract: A description is presented of the constraints on the library and the schedule for the module allocation graphs to be comparability graphs. An exact algorithm for module allocation on module allocation graphs that are comparability graphs is presented. This algorithm takes into account the first-order effects of the interconnection weights. >

10 citations


Cited by
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Journal Article•DOI•
W. W. Muir1•
01 May 1981
TL;DR: This chapter discusses Detecting Influential Observations and Outliers, a method for assessing Collinearity, and its applications in medicine and science.
Abstract: 1. Introduction and Overview. 2. Detecting Influential Observations and Outliers. 3. Detecting and Assessing Collinearity. 4. Applications and Remedies. 5. Research Issues and Directions for Extensions. Bibliography. Author Index. Subject Index.

4,948 citations

Journal Article•DOI•
Jason Cong, Bin Liu, Stephen Neuendorffer1, Juanjo Noguera1, Kees Vissers1, Zhiru Zhang •
TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Abstract: Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

728 citations

Posted Content•
TL;DR: In this article, the authors analyse the effect of shocks using generalised spatio-temporal impulse responses and highlight the diffusion of shocks both over time (as with the conventional impulse responses) and over space.
Abstract: This paper provides a method for the analysis of the spatial and temporal diffusion of shocks in a dynamic system. We use changes in real house prices within the UK economy at the level of regions to illustrate its use. Adjustment to shocks involves both a region specific and a spatial effect. Shocks to a dominant region - London - are propagated contemporaneously and spatially to other regions. They in turn impact on other regions with a delay. We allow for lagged effects to echo back to the dominant region. London in turn is influenced by international developments through its link to New York and other financial centers. It is shown that New York house prices have a direct effect on London house prices. We analyse the effect of shocks using generalised spatio-temporal impulse responses. These highlight the diffusion of shocks both over time (as with the conventional impulse responses) and over space.

315 citations

Patent•
08 Mar 2007
TL;DR: In this paper, a linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrodes segments within the linear-gated electrode track, while ensuring adequate electrical isolation between the adjacent linear gated electrode segments.
Abstract: A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

217 citations

Patent•
Hidemitsu Naya1, Rikio Tomiyoshi1, Shigeo Moriyama1, Mutsumi Kikuchi1, Kotaro Shimamura1 •
20 Aug 2001
TL;DR: In this article, a storage area network is used to connect the semiconductor manufacturing apparatus, the inspection apparatus, and the commonly used storage device in a semiconductor production system, which can be used to communicate a large volume of image data or design data at high speed.
Abstract: A semiconductor production system has a semiconductor manufacturing apparatus having an exposure unit, a control unit for controlling the exposure unit and a storage device; a semiconductor inspection apparatus having an observation unit, a control unit for controlling the observation unit and a storage device; and a storage device commonly used by the semiconductor manufacturing apparatus and the semiconductor inspection apparatus. The manufacturing apparatus, the inspection apparatus and the commonly used storage device are interconnected via a storage area network. With the semiconductor manufacturing apparatus and the storage device linked together via the storage area network, a large volume of image data or design data can be communicated at high speed, thus improving the system throughput.

209 citations