A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.

Stacked multi-chip modules and method of manufacturing

Several aspects of the multichip module technology, including its functions, leverages, applications, and markets, are reviewed All the packaging technologies used in multichip, such as sealing and encapsulation, heat removal, chip level connections, thin film, ceramic, and printed wiring, are discussed The module corrections and electrical testing used in forming a high-performance or portable system are also discussed >

Multichip packaging-a tutorial

Some trends for power electronic converters are evaluated, with emphasis on component and subcircuit technology, power converter technology, and integrated converter technology. Possible future trends are also considered. It is noted that important advances might come from the use and further development of nonlinear electromagnetic materials that have not been customary to power electronics in the past as well as from novel packaging and integration concepts. >

Some present and future trends in power electronic converters

A high-density laminated connector comprises a plurality of layers of rigid dielectric material which are laminated together. The rigid construction of the connector permits precise dimensions of the connecter and, thus, accurate attachment of adjacent circuit boards. The dielectric contains traces which are joined to contact pads, connecting the traces to adjacent circuit boards. The contact pads are comprised of soft gold, solder, and various elastomeric materials. The use of soft gold contacts allows the connector to be easily removed from the adjacent circuit board. Alternatively, the rigid dielectric layers contain recesses where the contact pads are placed. This ensures physical alignment of the circuit board and the connector, so that dimensional integrity is maintained when pressure is applied to the connector. The traces within the connector can be of a varied width, pitch, and direction. Thus, right-angle interconnections can be made. Cross-traces can be placed on each individual layer of dielectric or vias made through the dielectric layers, to interconnect traces. The trace width can be economically and accurately narrowed to produce high aspect ratios and thus provide high signal density.

High-density/long-via laminated connector

This paper presents a solution methodology for multiobjective optimization problems in the context of models for the placement of components on printed wiring boards (PWB's). The methodology combines the use of a flow and heat transfer solver, a genetic algorithm for the adaptive search of optimal or near-optimal solutions, and a multiobjective optimization strategy [Pareto optimization or multiattribute utility analysis (MUA)]. Using as the optimization criterion, the minimization of an estimate of the failure rate of the system of components due to thermal overheating (via an Arrhenius relation), the effectiveness of the present solution methodology is demonstrated by reference to a case with known optimal solutions. The results obtained using the same solution methodology for a multiobjective optimization problem (a variation of the case study) involving the minimization of the aforementioned total failure rate of the system as well as the minimization of the total wiring length (given some interconnectivity requirements) are presented and discussed for both Pareto optimization and MUA.

Multiobjective optimal placement of convectively cooled electronic components on printed wiring boards

Aspects of electronic packaging for mainframe applications are reviewed. A new generation of microwiring boards has been introduced, based on Cu/polymer layers on a polyimide base or metal/polymer layers on a multilayer ceramic or silicon base for high-end technologies. Advanced multilayer printed circuit boards will fulfil the requirements for low-end applications for the late 90s. In order to satisfy the desired reduction in line delay by packaging components on both sides of large-size wiring substrates, wiring technology is being challenged by miniaturized line structures and increased wiring density. High circuit integration, associated with revolutionary developments in device technology, reduction in chip-feature size, and a packaging technology based on multichip modules, has led to a significant increase in power dissipation and related flux. >

W. Koschnick

Papers

Electronic packaging in the 1990s: the perspective from Europe