High-level synthesis systems start with an abstract behavioral specification of a digital system and find a register-transfer level structure that realizes the given behavior. The various tasks involved in developing a register-transfer level structure from an algorithmic level specification are described. In particular, it is shown how the high-level synthesis task can be decomposed into a number of distinct but not independent subtasks. The techniques that have been developed for solving those subtasks are presented. Areas related to high-level synthesis that are still open problems are examined. >

The high-level synthesis of digital systems

This paper presents a unifying procedure, called Facet, for the automated synthesis of data paths at the register-transfer level. The procedure minimizes the number of storage elements, data operators, and interconnection units. A design generator named Emerald, based on Facet, was developed and implemented to facilitate extensive experiments with the methodology. The input to the design generator is a behavioral description which is viewed as a code sequence. Emerald provides mechanisms for interactively manipulating the code sequence. Different forms of the code sequence are mapped into data paths of different cost and speed. Data paths for the behavioral descriptions of the AM2910, the AM2901, and the IBM System/370 were produced and analyzed. Designs for the AM2910 and the AM2901 are compared with commercial designs. Overall, the total number of gates required for Emerald's designs is about 15 percent more than the commercial designs. The design space spanned by the behavioral specification of the AM2901 is extensively explored.

Automated Synthesis of Data Paths in Digital Systems

Novel algorithms for the simultaneous cost/resource-constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed. The entire allocation process can be formulated as a two-dimensional placement problem of microinstructions in space and time. This formulation readily lends itself to the use of a variety of heuristics for solving the allocation problem. The authors present simulated-annealing-based algorithms which provide excellent solutions to this formulation of the allocation problem. These algorithms operate under a variety of user-specifiable constraints on hardware resources and costs. They also incorporate conditional resource sharing and simultaneously address all aspects of the allocation problem, namely register, arithmetic unit, and interconnect allocation, while effectively exploring the existing tradeoffs in the design space. >

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Algorithms for hardware allocation in data path synthesis

A novel approach to automatic data path synthesis is presented. This approach features innovations in the synthesis process as well as in the system implementation. The synthesis process exhibits three new features. The first relates to a subtask that performs an expert analysis of the input data flow graph and attempts to evenly distribute operations requiring similar resources. This is done using a novel "load balancing" technique. The second consists of a global preselection of operator cells to fulfill an explicit speed constraint. Finally, the third deals with new techniques for register and multiplexer optimization. These features support extended design space search by taking an explicit performance specification into account. The system implementation is based on the LOOPS multiparadigm programming system. In this approach the overall task can be partitioned into complementary subtasks requiring different programming paradigms. These subtasks will be realized using an object-based paradigm, a knowledge-based expert system paradigm, a functional paradigm, or combinations of all three. Two complete examples are given to demonstrate the functionality of the system and to allow comparison with existing systems.

HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis

The article describes the status of work at IMEC on the Cathedral-II silicon compiler. The compiler was developed to synthesize synchronous multiprocessor system chips for digital signal processing. It is a continuation of work on the Cathedral-I operational silicon compiler for bit-serial digital filters. Cathedral-II is based on a ?meet in the middle? design method that encourages a total separation between system design and reusable silicon design. The CAD system includes a rule-based synthesis program, a procedural program, and a controller synthesis environment. Processors are synthesized in terms of modules called from automated reusable module generators. Chip layout is done on a floor planner. An expert subsystem verifies correctness during silicon design and generates functional and timing models for verification at the module and chip levels.

Cathedral-II: A Silicon Compiler for Digital Signal Processing

specification. Digital system design actually consists of many synthesis steps, each adding detail. The quality of designs produced by automatic synthesis programs are not yet adequate for production use. However, their use as a computer aid permitting designer interaction is becoming a realitv, 1 and promises further

Walker

Papers

Automatic Data Path Synthesis