Walt Kester

Bio: Walt Kester is an academic researcher from Analog Devices. The author has contributed to research in topics: Section (archaeology) & CMOS. The author has an hindex of 7, co-authored 52 publications receiving 560 citations.

Data Conversion Handbook

Abstract: 1. Fundamentals of Sampled Data Systems Coding and Quantizing DAC/ADC Ideal Static Transfer Functions Sampling Theory Data Converter AC errors and specifications 2. DAC Architectures and Origins Kelvin Divider String DACs R/2R DACs Segmented DACs Capacitor DACs Multiplying DACs Interpolating DACs Deglitching DAC outputs PWM DACs Sigma-Delta DACs Video DACs with lookup tables Digital potentiometers MicroDACs LogDACs 3. ADC Architectures and origins Low speed High speed Sigma-Delta 4. Data Converter Process Technology 5. Testing Data Converters 6. Interfacing to ADCs and DACs 7. Data Conversion Support Circuits Sample-and-hold circuits Voltage references Analog switches and multiplexers 8. Applications Precision measurement and sensor conditioning Data acquisition subsystems Multichannel systems and multiplexing Data distribution systems using multiple DACs Digital pot applications Display electronics Audio Video Software radio and IF sampling Higher levels of integration DDS 9. Hardware Design Techniques for Mixed-Signal Systems Passive components Printed circuit board design issues Layout "Smart" Partitioning Grounding mixed signal devices Digital isolation techniques Filtering switching supply outputs Data converter overvoltage protection Thermal considerations EMI/RFI considerations Logic considerations Simulation and IBIS models Prototyping Evaluation Boards Appendix Index

Hardware Design Techniques

Abstract: Publisher Summary The current revolution in supply voltage reduction has been driven by demand for faster and smaller products at lower costs. This push has caused silicon geometries to drop from 2 pin in the early 1980s to 0.25 pin, which is used in today's latest microprocessor and IC designs. As feature sizes have become increasingly smaller, the voltage for optimum device performance has also dropped below the 5 V level. This is illustrated in the current microprocessors for personal computers, where the optimum core operating voltage is programmed externally using voltage identification (VID) pins, and can be as low as 1.3 V. The strong interest in lower voltage digital signal processing (DSP) is clearly visible in the shifting sales percentages for 5 V and 3.3 V parts. Sales growth for 3.3 V DSPs has increased at more than twice the rate of the rest of the DSP market (30% for all DSPs versus more than 70% for 3.3 V devices). This trend will continue as the high volume/high growth portable markets demand signal processors that contain all of the traits of the lower voltage DSPs.

A review of nanometer resolution position sensors: Operation and performance

Abstract: Position sensors with nanometer resolution are a key component of many precision imaging and fabrication machines. Since the sensor characteristics can define the linearity, resolution and speed of the machine, the sensor performance is a foremost consideration. The first goal of this article is to define concise performance metrics and to provide exact and approximate expressions for error sources including non-linearity, drift and noise. The second goal is to review current position sensor technologies and to compare their performance. The sensors considered include: resistive, piezoelectric and piezoresistive strain sensors; capacitive sensors; electrothermal sensors; eddy current sensors; linear variable displacement transformers; interferometers; and linear encoders.

Phase-Change Memory Optimization for Green Cloud with Genetic Algorithm

Abstract: Green cloud is an emerging new technology in the computing world in which memory is a critical component. Phase-change memory (PCM) is one of the most promising alternative techniques to the dynamic random access memory (DRAM) that faces the scalability wall. Recent research has been focusing on the multi-level cell (MLC) of PCM. By precisely arranging multiple levels of resistance inside a PCM cell, more than one bit of data can be stored in one single PCM cell. However, the MLC PCM suffers from the degradation of performance compared to the single-level cell (SLC) PCM, due to the longer memory access time. In this paper, we present a genetic-based optimization algorithm for chip multiprocessor (CMP) equipped with PCM memory in green clouds. The proposed genetic-based algorithm not only schedules and assigns tasks to cores in the CMP system, but also provides a PCM MLC configuration that balances the PCM memory performance as well as the efficiency. The experimental results show that our genetic-based algorithm can significantly reduce the maximum memory usage by 76.8 percent comparing with the uniform SLC configuration, and improve the efficiency of memory usage by 127 percent comparing with the uniform 4 bits/cell MLC configuration. Moreover, the performance of the system is also improved by 24.5 percent comparing with the uniform 4 bits/cell MLC configuration in terms of total execution time.

Stabilized Feedback Amplifiers

Abstract: This paper describes and explains the theory of the feedback principle and then demonstrates how stability of amplification and reduction of modulation products, as well as certain other advantages, follow when stabilized feedback is applied to an amplifier. The underlying principle of design by means of which singing ia avoided is next set forth. The paper concludes with some examples of results obtained on amplifiers which have been built employing this new principle. The carrier-in-cable system dealt with in a companion paper1 involves many amplifiers in tandem with many telephone channels passing through each amplifier and constitutes, therefore, an ideal field for application of this feedback principle. A field trial of this system was made at Morristown, New Jersey, in which seventy of these amplifiers were operated in tandem. The results of this trial were highly satisfactory and demonstrated conclusively the correctness of the theory and the practicability of its commercial application.

Morphable memory system: a robust architecture for exploiting multi-level phase change memories

Abstract: Phase Change Memory (PCM) is emerging as a scalable and power efficient technology to architect future main memory systems. The scalability of PCM is enhanced by the property that PCM devices can store multiple bits per cell. While such Multi-Level Cell (MLC) devices can offer high density, this benefit comes at the expense of increased read latency, which can cause significant performance degradation. This paper proposes Morphable Memory System (MMS), a robust architecture for efficiently incorporating MLC PCM devices in main memory. MMS is based on observation that memory requirement varies between workloads, and systems are typically over-provisioned in terms of memory capacity. So, during a phase of low memory usage, some of the MLC devices can be operated at fewer bits per cell to obtain lower latency. When the workload requires full memory capacity, these devices can be restored to high density MLC operation to have full main-memory capacity. We provide the runtime monitors, the hardware-OS interface, and the detailed mechanism for implementing MMS. Our evaluations on an 8-core 8GB MLC PCM-based system show that MMS provides, on average, low latency access for 95% of all memory requests, thereby improving overall system performance by 40%.

Signal isolators using micro-transformers

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.