Walter Riess

Bio: Walter Riess is an academic researcher from IBM. The author has contributed to research in topics: Field-effect transistor & Nanowire. The author has an hindex of 36, co-authored 96 publications receiving 6101 citations. Previous affiliations of Walter Riess include GlobalFoundries.

Quantum optimization using variational algorithms on near-term quantum devices

Abstract: Universal fault-tolerant quantum computers will require error-free execution of long sequences of quantum gate operations, which is expected to involve millions of physical qubits. Before the full power of such machines will be available, near-term quantum devices will provide several hundred qubits and limited error correction. Still, there is a realistic prospect to run useful algorithms within the limited circuit depth of such devices. Particularly promising are optimization algorithms that follow a hybrid approach: the aim is to steer a highly entangled state on a quantum system to a target state that minimizes a cost function via variation of some gate parameters. This variational approach can be used both for classical optimization problems as well as for problems in quantum chemistry. The challenge is to converge to the target state given the limited coherence time and connectivity of the qubits. In this context, the quantum volume as a metric to compare the power of near-term quantum devices is discussed. With focus on chemistry applications, a general description of variational algorithms is provided and the mapping from fermions to qubits is explained. Coupled-cluster and heuristic trial wave-functions are considered for efficiently finding molecular ground states. Furthermore, simple error-mitigation schemes are introduced that could improve the accuracy of determining ground-state energies. Advancing these techniques may lead to near-term demonstrations of useful quantum computation with systems containing several hundred qubits.

Nanoparticle printing with single-particle resolution

Abstract: Bulk syntheses of colloids efficiently produce nanoparticles with unique and useful properties. Their integration onto surfaces is a prerequisite for exploiting these properties in practice. Ideally, the integration would be compatible with a variety of surfaces and particles, while also enabling the fabrication of large areas and arbitrarily high-accuracy patterns. Whereas printing routinely meets these demands at larger length scales, we have developed a novel printing process that enables positioning of sub-100-nm particles individually with high placement accuracy. A colloidal suspension is inked directly onto printing plates, whose wetting properties and geometry ensure that the nanoparticles only fill predefined topographical features. The dry particle assembly is subsequently printed from the plate onto plain substrates through tailored adhesion. We demonstrate that the process can create a variety of particle arrangements including lines, arrays and bitmaps, while preserving the catalytic and optical activity of the individual nanoparticles.

Realization of a silicon nanowire vertical surround-gate field-effect transistor.

Abstract: Semiconducting nanowires have recently attracted considerable attention. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well as for technology. A variety of technical applications, such as nanowires as parts of sensors, and electronic and photonic devices have already been demonstrated. In particular, electronic applications come more and more into focus, as the ongoing miniaturization in microelectronics demands new innovative solutions. Semiconducting nanowires, in particular epitaxially grown silicon (Si) nanowires, are considered as promising candidates for post-CMOS (CMOS: complementary metal–oxide semiconductor) logic elements owing to their potential compatibility with existing CMOS technology. One major advantage of vapor–liquid– solid(VLS-) grown nanowires compared to top-down fabricated devices is that they have well-defined surfaces. This reduces surface scattering, an issue which becomes important for devices on the nanoscale. Moreover, epitaxially grown nanowires circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-and-place approach, where devices are fabricated by manipulating horizontally lying VLS-grown nanowires. The first step towards a technical realization of a nanowire logic element is the design and manufacturing of a nanowire transistor. The epitaxial growth of vertical nanowires offers advantages over other approaches: For example, the transistor gate can be wrapped around the vertically oriented nanowire. Such a wrapped-around gate allows better electrostatic gate control of the conducting channel and offers the potential to drive more current per device area than is possible in a conventional planar architecture. In this Communication, a generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described. Exemplarily, we used Si nanowires and present a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device. Figure 1a shows a schematic cross section through a conventional p-type MOSFET. In such a device, an inversion channel can be created close to the gate by applying a negative gate voltage. This forms a conducting channel that connects the p-doped regions between the source and drain contacts electrically. Using this concept, a silicon nanowire VS-FET would ideally require a nanowire that is n-doped in the region of the gate and p-doped elsewhere. Unfortunately, such a p-n-p structure with abrupt transitions appears difficult to realize if the nanowires are grown by means of the vapor–liquid–solid mechanism using gold as a catalyst. The difficulty here is that the dopant atoms, which are dissolved in the catalyst droplet, might act as a reservoir, thus creating a graded transition when switching to another dopant. Therefore, we used a structure consisting of an n-doped silicon nanowire grown on a p-type substrate (see Figure 1b). If the gate–drain and gate–source distances are not too long, it is electrostatically still possible to create an inversion channel along the length of the entire wire. In the proposed configuration, the p–n junction at the source contact (Figure 1a) is replaced by a Au/n-Si Schottky contact at the nanowire tip. In order to investigate the influence of the Au/n-Si Schottky contact on the nanowire (current–voltage) I–V characteristics, an array of n-doped nanowires vertically grown on an n-type (111)-oriented substrate was imbedded in a spin-coated SiO2 matrix. After removing the thin SiO2 coverage from the Au tips by a short reactive ion etching, contacts 0.6 mm in size were defined by evaporating aluminum onto the sample, such that approximately 10 nanowires were contacted in parallel. The temperature-dependent measurements (shown in Figure 2) were performed by applying a voltage to the Si substrate, while the Al top contact was held at a constant potential. The measurements reveal a strong rectifying behavior with a thermally activated current possessing an activation energy of 0.6 eV. This can be explained by the Au/n-Si Schottky contact dominating the I–V behavior. The fact that the Schottky contact is forward-biased for negative voltages furthermore proves that, as expected, electrons act as majority charge carries. Figure 1. Schematics of a) a conventional p-channel MOSFET and b) a silicon nanowire vertical surround-gate field-effect transistor.

Toward Nanowire Electronics

Abstract: This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

Progress, Challenges, and Opportunities in Two-Dimensional Materials Beyond Graphene

Abstract: Graphene’s success has shown that it is possible to create stable, single and few-atom-thick layers of van der Waals materials, and also that these materials can exhibit fascinating and technologically useful properties. Here we review the state-of-the-art of 2D materials beyond graphene. Initially, we will outline the different chemical classes of 2D materials and discuss the various strategies to prepare single-layer, few-layer, and multilayer assembly materials in solution, on substrates, and on the wafer scale. Additionally, we present an experimental guide for identifying and characterizing single-layer-thick materials, as well as outlining emerging techniques that yield both local and global information. We describe the differences that occur in the electronic structure between the bulk and the single layer and discuss various methods of tuning their electronic properties by manipulating the surface. Finally, we highlight the properties and advantages of single-, few-, and many-layer 2D materials in...

Tunnel field-effect transistors as energy-efficient electronic switches

Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Synthesis of Light-Emitting Conjugated Polymers for Applications in Electroluminescent Devices

Abstract: A review was presented to demonstrate a historical description of the synthesis of light-emitting conjugated polymers for applications in electroluminescent devices. Electroluminescence (EL) was first reported in poly(para-phenylene vinylene) (PPV) in 1990 and researchers continued to make significant efforts to develop conjugated materials as the active units in light-emitting devices (LED) to be used in display applications. Conjugated oligomers were used as luminescent materials and as models for conjugated polymers in the review. Oligomers were used to demonstrate a structure and property relationship to determine a key polymer property or to demonstrate a technique that was to be applied to polymers. The review focused on demonstrating the way polymer structures were made and the way their properties were controlled by intelligent and rational and synthetic design.

High Performance Multilayer MoS2 Transistors with Scandium Contacts

Abstract: While there has been growing interest in two-dimensional (2-D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancy due to the lack of a complete picture of their performance potential. The focus of this article is on contacts. We demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2-D material can be harvested. Using scandium contacts on 10-nm-thick exfoliated MoS2 flakes that are covered by a 15 nm Al2O3 film, high effective mobilities of 700 cm2/(V s) are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. In fact, the apparent linear dependence of current on drain voltage had mislead researchers to believe that a truly Ohmic contact had already been achieved, a miscon...