Wan Mohd Hashimi Wan Mohamad Sharif

Bio: Wan Mohd Hashimi Wan Mohamad Sharif is an academic researcher from Universiti Teknologi MARA. The author has contributed to research in topics: NAND gate & Logic gate. The author has co-authored 1 publications.

Hybrid memristor-CMOS implementation of logic gates design using LTSpice

Abstract: In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.

A Cryogenic Artificial Synapse based on Superconducting Memristor

Abstract: Spiking neural network (SNN) has emerged as the most biologically accurate approach for information encoding in neuromorphic computing. Cryogenic neuromorphic hardware, which offers exceptional energy efficiency and speed, has recently gained enormous attention among the neuromorphic community. An approach to build such neuromorphic hardware is to use a conductance asymmetric superconducting quantum interference device (CA-SQUID) that has non-volatile and variation- robust dual-resistive behavior and thereby, is referred to as a superconducting memristor (SM). Here, we utilize this unique device to design an SM-based artificial synapse topology for neuromorphic applications. The proposed synapse structure, combined with an SM-based neuron, demonstrates neurosynaptic behavior with enhanced reconfigurability. Our design features eight different non-volatile levels of synaptic strength, utilizing combinations of distinct resistance levels of three SMs, exhibiting an estimated programming power of 8.5 pW. This weight storage feature enables better reconfigurability compared to the existing superconducting synapse structures that utilized fixed resistors and inductors. Additionally, this synapse can be further fine-tuned to dynamically access a wide range of synaptic strengths by using an external bias current. Our study provides valuable insights into the system-level integration of the neuron-synaptic architecture.