Wang Xiayu

Bio: Wang Xiayu is an academic researcher from Xidian University. The author has contributed to research in topics: Signal & Charge pump. The author has an hindex of 2, co-authored 6 publications receiving 10 citations.

A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR

Abstract: An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB $\Omega $ , and 4.68 pA/ $\surd $ Hz respectively. The proposed AFE circuit, which is fabricated in $0.18~\mu \text{m}$ CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

A High Linearity TDC With a United-Reference Fractional Counter for LiDAR

Abstract: A united-reference fractional counter (URFC) is proposed for multi-level time-to-digital converters (TDCs) used in direct time-of-flight (dToF) light detection and ranging (LiDAR) applications. The URFC combines the integer counter and the second-level interpolation in one functional block that derives both the integer part and the fractional part from the same synchronization result. Thus the proposed TDC has a more robust structure to deal with misalignment errors, and measurement results from different levels can be perfectly matched. High linearity and high precision can be guaranteed because of the united reference without calibration. The response time of the URFC decreases to hundreds of picoseconds, which makes it suitable for all output pulses from the avalanche photodiode. A TDC with the proposed URFC was implemented in 65nm standard CMOS technology with a detection range of 2.5μs (~375m) and a single shot precision of 27.63ps (~4.0mm). The power consumption is 51.4mW with a reference clock at 200MHz and a repetition rate at 999kHz. The INL and DNL are ±2.751 LSB and ±1.679 LSB, respectively.

A CMOS Peak Detect and Hold Circuit With Auto-Adjust Charging Current for NS-Scale Pulse ToF Lidar Application

Abstract: This paper presents a novel CMOS peak detect and hold (PDH) circuit scheme for pulsed time of flight (ToF) Lidar application The proposed PDH circuit, which is one part of analog front end (AFE) circuit of Lidar receiver, is used to widen the narrow input pulse width, aiming to easily digitize the pulse amplitude through a low-speed and low-cost ADC in pulsed ToF Lidar application The reset voltage clamped to the common-mode level of the input pulse voltage is beneficial to reduce the pedestal error voltage Meanwhile, the auto-adjust charging current scheme is employed to decrease the peak error through rejecting the overshoot voltage in the proposed PDH circuit The circuit was implemented and fabricated in a 65-nm CMOS technology The proposed PDH circuit can detect the pulse voltage with a pulse amplitude range from ~20 mV to ~500 mV and a minimum pulse width of 5 ns The measured results show that the maximum absolute and relative errors are less than 16 mV and 45%, respectively The layout area of the proposed PDH circuit is equal to $017\times 014$ mm2

Time digital conversion system based on synchronous timing sequence

Abstract: The invention discloses a time digital conversion system based on a synchronous timing sequence. The system comprises a bias module, a multi-phase clock synchronization module, an interpolation quantization module, a tracking and quantization module, a counter module and a data integration output module, wherein the bias module is connected with the first signal input end; the multi-phase clock synchronization module is connected with the second signal input end, the third signal input end and the bias module; the interpolation quantization module, the counter module and the tracking and quantization module are connected with the multi-phase clock synchronization module; and the tracking and quantization module is further connected with the second signal input end, the third signal input end, the bias module, the interpolation quantization module, the counter module, the tracking and quantization module and the data integration output module. The multi-phase clock synchronization module is adopted, so that the signal competition and risk problems of an asynchronous system are avoided, the system error is reduced, the signal extraction and detection are all completed based on the multi-phase clock synchronization module, system errors caused by inter-layer data mismatch are avoided, and the detection precision is improved.

Fast locked delay chain phase-locked loop

Abstract: The invention discloses a fast locked delay chain phase-locked loop, which comprises a voltage-controlled delay chain, an acceleration locking control module, a phase discriminator, a charge pump anda loop filter; the voltage-controlled delay chain is connected with a clock input end; the acceleration locking control module is connected with the voltage-controlled delay chain; the phase discriminator is connected with the output end of the voltage-controlled delay chain and the output end of the acceleration locking control module; the charge pump is connected with the output end of the phasediscriminator and the output end of the acceleration locking control module; and the loop filter is connected with the output end of the charge pump and the input end of the voltage-controlled delaychain. The delay chain phase-locked loop provided by the invention can enable a system to quickly, stably and accurately enter a locked state.

Design Of Analog Cmos Integrated Circuits

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A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR

Abstract: An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB $\Omega $ , and 4.68 pA/ $\surd $ Hz respectively. The proposed AFE circuit, which is fabricated in $0.18~\mu \text{m}$ CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

A Transimpedance-to-Noise Optimized Analog Front-End With High PSRR for Pulsed ToF Lidar Receivers

Abstract: This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB $\boldsymbol {\Omega }$ transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a $0.11\, \boldsymbol {\mu }\text{m}$ CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving $50 \boldsymbol {\Omega } $ loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 $\boldsymbol {\mu }\text{m}\,\,\boldsymbol {\times } 110\,\,\boldsymbol {\mu }\text{m}$ in area.

A Low-Noise and Wide Dynamic Range 15 MHz CMOS Receiver for Pulsed Time-of-Flight Laser Ranging

Abstract: A laser radar receiver channel targeted at pulsed time-of-flight laser radar applications using 5ns…20ns laser pulses at the 1550nm wavelength region has been designed. The receiver includes a transimpedance preamplifier, post-amplifiers and analog output buffer and has a bandwidth of 15MHz and input reduced total equivalent current noise of ~3nArms without the contribution of the APD noise. The receiver supports both the single shot and transient recording operation modes. By utilizing the time domain compensation methods, the single shot timing walk is at the level of +/−100ps within a wide dynamic range of 1: 36 000 of the received echo amplitudes. It is demonstrated that the designed receiver allows the pulsed time-of-flight measurement in the single shot mode to non-cooperative targets up to distances of several hundreds of meters with a laser pulse power of 4 W and receiver aperture of 20mm.

A CMOS Optoelectronic Receiver IC with an On-Chip Avalanche Photodiode for Home-Monitoring LiDAR Sensors

Abstract: This paper presents an optoelectronic receiver (Rx) IC with an on-chip avalanche photodiode (APD) realized in a 0.18-μm CMOS process for the applications of home-monitoring light detection and ranging (LiDAR) sensors, where the on-chip CMOS P+/N-well APD was implemented to avoid the unwanted signal distortion from bondwires and electro-static discharge (ESD) protection diodes. Various circuit techniques are exploited in this work, such as the feedforward transimpedance amplifier for high gain, and a limiting amplifier with negative impedance compensation for wide bandwidth. Measured results demonstrate 93.4-dBΩ transimpedance gain, 790-MHz bandwidth, 12-pA/√Hz noise current spectral density, 6.74-μApp minimum detectable signal that corresponds to the maximum detection range of 10 m, and 56.5-mW power dissipation from a 1.8-V supply. This optoelectronic Rx IC provides a potential for a low-cost low-power solution in the applications of home-monitoring LiDAR sensors.