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Wanyuan Qu

Bio: Wanyuan Qu is an academic researcher from KAIST. The author has contributed to research in topics: Computer science & Charge pump. The author has an hindex of 4, co-authored 7 publications receiving 142 citations.

Papers
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Journal ArticleDOI
TL;DR: This paper proposes a coarse-fine dual-loop architecture for the digital low drop-out (LDO) regulators with fast transient response and more than 200-mA load capacity and a digital controller is implemented to prevent contentions between the two loops.
Abstract: This paper proposes a coarse-fine dual-loop architecture for the digital low drop-out (LDO) regulators with fast transient response and more than 200-mA load capacity. In the proposed scheme, the output voltage is coregulated by two loops, namely, the coarse loop and the fine loop. The coarse loop adopts a fast current-mirror flash analog to digital converter and supplies high output current to enhance the transient performance, while the fine loop delivers low output current and helps reduce the voltage ripples and improve the regulation accuracies. Besides, a digital controller is implemented to prevent contentions between the two loops. Fabricated in a 28-nm Samsung CMOS process, the proposed digital LDO achieves maximum load up to 200 mA when the input and the output voltages are 1.1 and 0.9 V, respectively, with a chip area of 0.021 mm2. The measured output voltage drop of around 120 mV is observed for a load step of 180 mA.

92 citations

Journal ArticleDOI
Wanyuan Qu1, Shashank Singh2, Yong-Jin Lee2, Young-Suk Son, Gyu-Hyeong Cho1 
TL;DR: A design-oriented analysis (DOA) method is presented, which lends sufficient insights into various Miller compensation schemes, and a multistage amplifier capable of driving a large-capacitive load with low power consumption is presented.
Abstract: A design-oriented analysis (DOA) method is presented, which lends sufficient insights into various Miller compensation schemes. The method predicts the nondominant poles of the Miller-compensated amplifiers in an intuitive manner, and it serves as a good supplement to the conventional analysis. The usage of DOA is verified by the various design examples given in this paper. Guided by DOA, a multistage amplifier capable of driving a large-capacitive load ( $C_{L}$ ) with low power consumption is presented. This amplifier employs an active zero to extend its Miller loop bandwidth, thereby pushing the amplifier’s nondominant poles to high frequencies and achieving larger gain bandwidth (GBW). Fabricated in a 0.18- $\mu \text{m}$ CMOS process, the amplifier achieves 1.18-MHz GBW and 59.6° phase margin when driving an 18-nF $C_{L}$ , while consuming 69.6 $\mu \text{W}$ from a 1.2-V supply. The design shows improved figures-of-merit compared with the prior state-of-the-art Miller-compensated multistage amplifiers.

60 citations

Proceedings ArticleDOI
06 Mar 2014
TL;DR: The approach applies feedback theory and simplifies high-frequency Miller amplifiers, thereby reducing orders of circuits and improving insight, and is applicable to large-number-stage amplifiers.
Abstract: As process scales down, low-voltage, low-power, multistage amplifiers capable of driving a large capacitive load with wide bandwidth are becoming more important for various applications. The conventional frequency compensation methods, however, are based on cumbersome transfer function derivations or complicated local loop analysis, inhibiting intuitive understanding. An approach is presented in this paper, which generates insight for the poles and zeros through distinctive compensation analysis, and is applicable to large-number-stage amplifiers. The approach applies feedback theory and simplifies high-frequency Miller amplifiers, thereby reducing orders of circuits and improving insight.

27 citations

Journal ArticleDOI
TL;DR: In this paper, a fully integrated digitally assisted low-dropout regulator (LDO) for a NAND flash memory system is proposed and verified using 500-nm I/O CMOS transistors.
Abstract: In this paper, a fully integrated digitally assisted low-dropout regulator (LDO) for a NAND flash memory system is proposed and verified using 500 nm I/O CMOS transistors. By combining an amplifier (AMP)-based LDO with a comparator (CMP)-based LDO, the proposed LDO achieves both fast load response in the transient state and accurate regulation in the steady state, which are advantages of the CMP-based LDO and AMP-based LDO, respectively. Moreover, loop frequency stability is satisfied in a wide range of load currents between 0 and 150 mA by using the simple structure of the $g_{m}$ -boost cell to insert an auxiliary path. For an input voltage range of 2.3–3 V and an output voltage of 2.1 V, the measured output droop is 225 mV for a 150 mA load step in the load transition time of 20 ns with the total bias current of $81\,\mu {\rm{A}}$ . The fabricated prototype chip occupies $160\,\times \,610\,\mu {\rm{m}}^{2}$ with an on-chip output capacitor of 2 nF.

15 citations

Proceedings ArticleDOI
20 Feb 2022
TL;DR: In this article , a dynamic-body-biasing assisted correlated level shifting (CLS) technique was used to boost the DC gain of a single-stage floating-inverter amplifier with only one reservoir capacitor to above 66dB with minimal area overhead.
Abstract: Micro-power ΔΣ modulators are suitable for low-bandwidth, high-precision applications, such as smart sensors, biomedical signal processing and battery-powered IoT devices. They achieve high SNR by oversampling and noise shaping, but higher order loops have stability problems. The multistage noise-shaping (MASH) technique solves this problem by realizing a high-order NTF with several low-order stages. However, for the MASH structure to be effective, the loop filter integrators must have high gain to avoid quantization noise leakage. Conventionally, they are realized by high-gain OTAs with gain-boosted cascode [1].However, they draw static bias current, and their biasing and common mode feedback (CMFB) make them unattractive in duty-cycled operation in IoT applications due to the long settling time. The floating-inverter amplifier (FIA) [2] does not require biasing and CMFB, which makes it an attractive option for IoT applications. However, cascade topologies are needed to achieve high gain in [2–3], which increases complexity and area since each stage contributes a pole and requires a reservoir capacitor (CRES). An additional CRES is used in the output stage of [3] to optimize the settling performance and stability, which costs further area. This paper presents a dynamic-body-biasing assisted correlated level shifting (CLS) technique to boost the DC gain of a single-stage FIA with only one reservoir capacitor to above 66dB with minimal area overhead. This enables a fully dynamic MASH ADC that consumes 2.87μW while achieving 96.9dB DR and 94.0dB SNDR in 1kHz BW at an OSR of 125×, resulting in a SNDR-based Schreier FoM of 179.4dB.

4 citations


Cited by
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Journal ArticleDOI
TL;DR: This work presents a power- and area-efficient three-stage amplifier that is able to drive a large capacitive load and achieves an optimized tradeoff between the frequency and the Q-factor of the complex poles.
Abstract: This work presents a power- and area-efficient three-stage amplifier that is able to drive a large capacitive load. Removing the inner Miller capacitor and employing cascode Miller compensation in the outer compensation loop could extend the complex-pole frequency of a three-stage amplifier, but result in a high Q-factor. A local impedance attenuation block consisting of a series RC network is proposed to control the complex poles. This block attenuates the high-frequency resistance at the second-stage output and achieves an optimized tradeoff between the frequency and the Q-factor of the complex poles. As the low-frequency resistance remains unchanged, a high dc gain is maintained. Implemented in 0.13 $\mu$ m CMOS process, the proposed design occupies an area of 0.0032 mm 2 and consumes a quiescent current of 10.5 $\mu$ A. When driving a 560 pF capacitive load, it achieves a unity-gain frequency of 3.49 MHz, an average slew rate of 0.86 V/ $\mu$ s, and an average settling time of 0.9 $\mu$ s.

89 citations

Journal ArticleDOI
TL;DR: This paper presents an analog-assisted (AA) output-capacitor-free digital low-dropout (D-LDO) regulator with tri-loop control, and a nonlinear coarse word control is designed for the carry-in/out operations.
Abstract: This paper presents an analog-assisted (AA) output-capacitor-free digital low-dropout (D-LDO) regulator with tri-loop control. For responding to instant load transients, the proposed high-pass AA loop momentarily adjusts the unit current of the power switch array, and significantly reduces the voltage spikes. In the proposed D-LDO, the overall 512 output current steps are divided into three sub-sections controlled by coarse/fine loops with carry-in/out operations. Therefore, the required shift register (SR) length is reduced, and a 9-bit output current resolution is realized by using only 28-SR bits. Besides, the coarse-tuning loop helps to reduce the recovery time, while the fine-tuning loop improves the output accuracy. To eliminate the limit cycle oscillation and reduce the quiescent current, a freeze mode is added after the fine-tuning operation. To reduce the output glitches and the recovery time, a nonlinear coarse word control is designed for the carry-in/out operations. The D-LDO is fabricated in a 65-nm general purpose CMOS process. A maximum voltage undershoot/overshoot of 105 mV is measured with a 10-mA/1-ns load step and a total capacitor of only 100 pF. Thus, the resulting figure-of-merit is 0.23 ps.

67 citations

Journal ArticleDOI
Wanyuan Qu1, Shashank Singh2, Yong-Jin Lee2, Young-Suk Son, Gyu-Hyeong Cho1 
TL;DR: A design-oriented analysis (DOA) method is presented, which lends sufficient insights into various Miller compensation schemes, and a multistage amplifier capable of driving a large-capacitive load with low power consumption is presented.
Abstract: A design-oriented analysis (DOA) method is presented, which lends sufficient insights into various Miller compensation schemes. The method predicts the nondominant poles of the Miller-compensated amplifiers in an intuitive manner, and it serves as a good supplement to the conventional analysis. The usage of DOA is verified by the various design examples given in this paper. Guided by DOA, a multistage amplifier capable of driving a large-capacitive load ( $C_{L}$ ) with low power consumption is presented. This amplifier employs an active zero to extend its Miller loop bandwidth, thereby pushing the amplifier’s nondominant poles to high frequencies and achieving larger gain bandwidth (GBW). Fabricated in a 0.18- $\mu \text{m}$ CMOS process, the amplifier achieves 1.18-MHz GBW and 59.6° phase margin when driving an 18-nF $C_{L}$ , while consuming 69.6 $\mu \text{W}$ from a 1.2-V supply. The design shows improved figures-of-merit compared with the prior state-of-the-art Miller-compensated multistage amplifiers.

60 citations

Journal ArticleDOI
TL;DR: Analytical treatments of the nested-current-mirror technique in terms of performance limits and robustness reveal that the NCM amplifier can surpass the fundamental power-efficiency limit set by the basic differential-pair (DP) amplifier.
Abstract: For better area and power efficiencies, rail-to-rail-output single-stage amplifiers are a potential replacement of their multi-stage counterparts, especially for display applications that entail massive buffer amplifiers in their column drivers. This paper describes a nested-current-mirror (NCM) technique for a single-stage amplifier to achieve substantial enhancements of DC gain, gain-bandwidth product (GBW) and slew rate (SR). Specifically, NCM is customizable for different mirror steps, and sub mirror ratios, to balance the performance metrics and capacitive-load ( ${\rm C}_{\rm L}$ ) drivability, avoiding any compensation passives while preserving a rail-to-rail output swing. Analytical treatments of the NCM technique in terms of performance limits and robustness reveal that the NCM amplifier can surpass the fundamental power-efficiency limit set by the basic differential-pair (DP) amplifier. Two prototypes, 3-step and 4-step NCM amplifiers, were fabricated in 0.18 $\mu$ m CMOS for systematic comparison with the DP amplifier. The former represents a robust design exhibiting 72 dB DC gain and 0.0028–0.27 MHz GBW over 0.15–15 nF ${\rm C}_{\rm L}$ with $> $ 80 $^{\circ}$ phase margin (PM). The latter embodies an aggressive design attaining 84 dB DC gain and 0.013–1.24 MHz GBW over 0.15–15 nF ${\rm C}_{\rm L}$ with $> $ 62 $^{\circ}$ PM. All amplifiers were sized for the same area (0.0013 mm $_{2}$ ) and power (3.6 $\mu$ W).

57 citations

Journal ArticleDOI
TL;DR: A recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude is presented.
Abstract: This paper presents a recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude. The proposed RLDO enables a practical digital replacement to analog LDOs by using an SAR-like binary search algorithm in a coarse loop and a sub-LSB pulse width modulation duty control scheme in a fine loop. A proportional-derivative compensation scheme is employed to ensure stable operation independent of load current, the size of the output decoupling capacitor, and clock frequency. Implemented in 0.0023 mm2 in 65 nm CMOS, the 7-bit RLDO achieves, at a 0.5-V input, a response time of 15.1 ns with a figure of merit of 199.4 ps, along with stable operation across a 20 000 $\times $ dynamic load range.

57 citations