This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of $-100\;\text{dBc/Hz}$ at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz.

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A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier

In this paper, the design and analysis of CMOS multicascode configuration with noise reduction topology are proposed. Two low power and miniature low-noise amplifiers (LNAs) were designed and fabricated for demonstration. One with cascode device was designed at V -band in 65-nm process, and the other with triple-cascode structure was fabricated at Q -band in 0.13-? m technology. To minimize the noise figure and maximize the small-signal gain, inductors are designed and placed between transistors of the cascode and triple-cascode configurations. Based on this approach, the Q-band LNA has a gain of 14.3 dB and a noise figure of 3.8 dB at 38 GHz, with a power consumption of 28.8 mW. The V-band LNA presents a gain of 14.4 dB and a noise figure of 4.5 dB at 54.5 GHz, with a power consumption of 10 mW. The chip size of the V- and Q-band LNAs are 0.55 × 0.45 mm2 and 0.42 × 0.6 mm2, including all the testing pads. Compared with the conventional cascode LNAs, the proposed cascode LNA shows better noise figure and lower power consumption whereas the triple-cascode LNA features higher gain performance.

Millimeter-Wave Low Power and Miniature CMOS Multicascode Low-Noise Amplifiers with Noise Reduction Topology

We demonstrate a subharmonic resistive graphene FET mixer utilizing the symmetrical channel-resistance versus gate-voltage characteristic. A down-conversion loss of 24 dB is obtained with fRF = 2 GHz, fLO= 1.01 GHz, and fIF= 20 MHz in a 50- Ω-impedance system. Unlike conventional subharmonic resistive FET mixers, this type of mixer operates with only one transistor and does not need any balun at the local oscillator (LO) port, which makes it more compact.

https://publications.lib.chalmers.se/records/fulltext/local_146694.pdf

A Subharmonic Graphene FET Mixer

This paper presents two 4-bit (16-phase) mm-wave vector modulator phase shifters exploiting a novel in-phase and quadrature signal generator that consists of a single-input double-output cascode amplifier incorporating a lumped-element coupled-line quadrature coupler. The two circuit implementations have been designed and fabricated in a 28 nm fully depleted silicon-on-insulator CMOS. The first (PS1) achieves a higher gain and the second (PS2) has a more compact area (reduced to about 50%). Each consumes 18 mA from a 1.2 V supply. PS1 exhibits an average gain of 2.3 dB at 87.4 GHz and $B_{3\text {dB}}$ from 78.8 to 92.8 GHz; rms gain error of 1.68 dB at 87.4 GHz and $B_{3\text {dB}}$ ; rms phase error of 9.4° at 87.4 GHz and $B_{3\text {dB}}$ ; $S_{11} dB in $B_{3\text {dB}}$ ; average $P_{1\text {dB}}$ of −7 dBm; and average noise figure (NF) equal to 10.8 dB at 87 GHz. PS2 exhibits an average gain of 0.83 dB at 89.2 GHz and $B_{3\text {dB}}$ from 80.2 to 96.8 GHz; rms gain error of 1.46 dB at 89.2 GHz and $B_{3\text {dB}}$ ; rms phase error of 11.2° at 89.2 GHz and $B_{3\text {dB}}$ ; $S_{11} dB in $B_{3\text {dB}}$ ; average $P_{1\text {dB}}$ of −6 dBm; and average NF of 11.9 dB at 89 GHz.

Two mm-Wave Vector Modulator Active Phase Shifters With Novel IQ Generator in 28 nm FDSOI CMOS

This paper presents a transformer-based poly-phase network to generate fully differential quadrature signals with low loss, compact area, and high-precision magnitude and phase balance over an ultra-wide bandwidth. A fully differential high-coupling 8-port folded transformer-based quadrature hybrid serves as the basic building block for the poly-phase unit stage to achieve significant size reduction and low loss. Multiple poly-phase unit stages can be cascaded to form the multistage poly-phase network to substantially extend the quadrature signal generation bandwidth. The designs of the high-coupling transformer-based quadrature hybrid, the poly-phase unit stage, and the multistage transformer-based poly-phase network are presented with the closed-form design equations in this paper. As a proof-of-concept design, a 3-stage transformer-based poly-phase network is implemented in a standard 65 nm bulk CMOS process with a core area of 772 $\mu$ m $\,\times\,$ 925 $\mu$ m. Measurement results of this poly-phase network over 3 independent samples demonstrate that the output In-Phase and Quadrature (I/Q) magnitude mismatch is less than 1 dB from 2.8 GHz to 21.8 GHz with a passive loss of 3.65 dB at 6.4 GHz. The measured output I/Q phase error is less than 10 $^{\circ}$ from 0.1 GHz to 24 GHz. The effective Image Rejection Ratio (IRR) based on the measured I/Q balancing is more than 30 dB from 3.7 GHz to 22.5 GHz. The 3-stage transformer-based poly-phase network design achieves high-quality quadrature signal generation over a first-ever one-decade bandwidth together with low-loss and compact area.

A Transformer-Based Poly-Phase Network for Ultra-Broadband Quadrature Signal Generation

An E-band high image-rejection sub-harmonic in-phase/quadrature (IQ) modulator for a high-order quadrature amplitude modulation (QAM) signal is designed and implemented on standard 65-nm CMOS technology To maintain high image-rejection ratio of the IQ modulator over a wide bandwidth for high data-rate application, a load-insensitive analysis and a local oscillator (LO) broadband 45° power splitter are proposed to achieve low amplitude and phase imbalanced structure In addition, the doubly balanced sub-harmonic Gilbert-cell mixer with the advantages of good LO leakage suppression has been selected in the mixer design The IQ modulator demonstrates a measured flat conversion gain of 0 ± 1 dB from 55 to 85 GHz The image rejection ratio is better than 40 dBc from 64 to 84 GHz For millimeter-wave communication applications, the IQ modulator is integrated with a four-stage power amplifier to form a direct-conversion transmitter The measured conversion gain of the transmitter is 33 dB and the measured saturated power is 11 dBm Via high image rejection and good LO suppression of the modulator, a 1024-QAM modulated signal with a data rate of 500 Mb/s and 17% error vector magnitude is successfully demonstrated at 65 GHz

1024-QAM High Image Rejection $E$ -Band Sub-Harmonic IQ Modulator and Transmitter in 65-nm CMOS Process

A compact and broadband 0.8-77.5-GHz passive distributed drain mixer using standard 0.13-mum CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of 5.5 plusmn1 dB from 0.8 to 77.5 GHz with a compact size of 0.67 0.58 mm2 . The output 1-dB compression point is -8.5 dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption.

Design and Analysis of a 0.8–77.5-GHz Ultra-Broadband Distributed Drain Mixer Using 0.13- $\mu$ m CMOS Technology

A 50-to-62 GHz injection-locked frequency divider (ILFD) with transformer feedback technique is designed in 0.13-mum CMOS technology for wide locking range. The measurement results show that the free-running frequency is 55.3 GHz and the total locking range is 12 GHz (>20%) at the input power level of 0 dBm while consuming 10.8 mW from a 0.9 V power supply. The phase noise of the divider is -124.93 dBc/Hz at 1 MHz offset from the carrier. This wide locking range ILFD is suitable for integration into a phase-lock-loop (PLL) system because of its small size and no need of extra control signal.

A 50-to-62GHz wide-locking-range CMOS injection-locked frequency divider with transformer feedback

A low voltage and low power 60 GHz low noise amplifier (LNA) using 90 nm standard MS/RF CMOS technology is presented in this paper. For the low voltage applications, a three-stage common source configuration is utilized. By using forward-body-bias, our LNA can operate at 0.7 V supply voltage and consumes 4.9 mW dc power while maintaining a peak gain of 13 dB at 55 GHz and 12.6 dB at 60 GHz with a compact chip size of 0.351 mm2. The 1-dB gain bandwidth is 54.5 to 61.0 GHz and the minimum noise figure is 6.3 dB at 64 GHz. This MMIC successfully demonstrates the forward-body-biased LNA in millimeter-wave frequency region with the lowest supply-voltage among the published LNAs around 60 GHz.

A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process

This paper presents a chip set of RF front-end circuits using 65-nm CMOS technology. The chip set includes a LNA, a down-conversion mixer, an up-conversion mixer and a medium power amplifier. The LNA has the 3-dB bandwidth from 68 to 75 GHz with a peak value of 17 dB. The down-conversion mixer has a conversion loss of better than −5 dB from 53 to 73 GHz at 4 dBm LO power. The up-conversion mixer has a conversion loss better than −5 dB from 53 to 75 GHz at 6 dBm LO power. The medium power amplifier delivers 5 dBm P 1dB and 6.7 dBm P sat at 71 GHz. These results show the potential of the 65-nm CMOS technology in high frequency circuit design.

Wei-Heng Lin

Papers

1024-QAM High Image Rejection $E$ -Band Sub-Harmonic IQ Modulator and Transmitter in 65-nm CMOS Process

Design and Analysis of a 0.8–77.5-GHz Ultra-Broadband Distributed Drain Mixer Using 0.13- $\mu$ m CMOS Technology

A 50-to-62GHz wide-locking-range CMOS injection-locked frequency divider with transformer feedback

A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process

A 71–76 GHz chip set for wireless communication in 65-nm CMOS technology