This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and techniques for minimizing these limitations are presented. For example, background calibration guarantees appropriate DTC gain, reducing spurs. Operating at 10 GHz the system achieves −38 dBc of integrated phase noise (280 fs RMS jitter) when a worst case fractional spur of −43 dBc is present. In-band phase noise is at the level of −104 dBc/Hz. The class-B VCO can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9 V and 1.8 V supplies.

A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

The high phase noise of ring oscillators has generally discouraged their use in RF synthesis. This paper introduces an integer-N synthesizer that employs a type-I loop to achieve a wide bandwidth, allowing the use of ring oscillators, and a master-slave sampling loop filter along with harmonic traps to suppress spurs. A 2.4 GHz prototype fabricated in 45 nm digital CMOS technology provides a loop bandwidth of 10 MHz and a spur level of $-\text{65}\;\text{dBc}$ . The phase noise is $-\text{114}\;\text{dBc}/\text{Hz}$ at 1 MHz offset.

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A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer

A fractional- $N$ sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional- $N$ PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional- $N$ PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional- $N$ mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.

A Fractional- N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its phase noise analysis, optimization, and design for future 5G wireless transceivers. The performance improvement of the cascaded phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption is theoretically presented and verified with measured results. The cascaded PLL is implemented using a first-stage fractional-N charge-pump PLL followed by a second-stage quadrature dividerless subsampling PLL. The fractional division in the first-stage PLL is implemented using a high-resolution phase mixer for lower quantization noise. Two prototypes of the single-stage PLL and the cascaded PLL were implemented in the 65-nm bulk CMOS process. The 26–32 GHz quadrature cascaded PLL consumes a total of 26.9 mW from 1-V supply and achieves less than 100-fs integrated jitter with −116.2 and −112.6-dBc/Hz phase noise at 1-MHz offset for the integer-N and the fractional-N modes, respectively. The fractional-N single-stage and cascaded PLLs achieve figure-of-merits of −230.58 and −248.75 dB, respectively.

A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture

Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm $^{2}$ , and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of $-$ 232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of $-$ 243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from $-$ 32 to $-$ 55 dBc.

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of -112 dBc/Hz at a 2.3 GHz output frequency. The analysis for the frequency synthesizer, especially for the nonlinear characteristics of the circuits, is proposed. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer consumes 9.6 mA and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

Recently, dividerless PLL architectures, including sub-sampling PLLs [1] and injection-locked PLLs [2], have been reported to achieve superior phase noise with respect to conventional PLL architectures. However, these dividerless architectures can only be operated in integer-N mode inherently. In order to operate in fractional-N mode, this work proposes a digital pulse-width modulator (DPWM) to modulate the pulse width of the input reference signal to synthesize the output frequency.

Wei-Sung Chang

Papers

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

21.2 A 2.3GHz fractional-N dividerless phase-locked loop with −112dBc/Hz in-band phase noise