We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of I on is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm

New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large-(digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET-device model incorporating the additional device/circuit-level non-idealities and multiple CNTs reported in the paper of Deng and Wong.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

Predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and physical correlations among model parameters, must be included. In addition, predictions across technology generations should be smooth to make continuous extrapolations. In this work, a new generation of predictive technology model (PTM) is developed to accomplish these goals. Based on physical models and early stage silicon data, PTM of bulk CMOS for 130nm to 32nm technology nodes is successfully generated. By tuning ten parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified: for NMOS, the error of I/sub on/ is 2% and for PMOS, it is 5%. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. A webpage has been established for the release of PTM (http://www.eas.asu.edu//spl sim/ptm).

New Generation of Predictive Technology Model for Sub-45nm Design Exploration

A predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures, such as the double-gate device (i.e., FinFET). Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10p for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available online at http://www.eas.asu.edu/~ptm.

Predictive technology model for nano-CMOS design exploration

Predictive MOSFET model is critical for early circuit design research In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10% for both NMOS and PMOS Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime PTM is available on line at http://wwweasasuedu/~ptm

Predictive Technology Model for Nano-CMOS Design Exploration

Statistical circuit analysis and optimization are crit- ical for robust nanoscale CMOS design. To accurately perform such analysis, primary process variation sources need to be identi- fied and modeled for further circuit simulation. In this work, a rig- orousmethodtoextractprocessvariationsfrominsituIVmeasure- ments is present. Transistor statistics are collected from a test chip fabricated in a 65-nm process. Gate length ( ), threshold voltage and mobility are recognized as the leading variation sources, due to the tremendous process challenges in lithography, channel doping, and the stress engineering. To decompose these variations, three critical IV points from the cut-off and linear re- gionsareidentified.Theextracted , and variationsarenor- mally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, accurate prediction of the change of drive current in all operation regions and process corners is achieved. The new extraction method guarantees excel- lent model matching with hardware for further statistical circuit analysis.

http://ieeexplore.ieee.org/iel5/66/4773471/04773506.pdf

Wei Zhao

Papers

New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

New Generation of Predictive Technology Model for Sub-45nm Design Exploration

Predictive technology model for nano-CMOS design exploration

Predictive Technology Model for Nano-CMOS Design Exploration

Rigorous Extraction of Process Variations for 65-nm