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Author

Weidong Xiong

Bio: Weidong Xiong is an academic researcher from Actel. The author has contributed to research in topics: Gate array. The author has an hindex of 2, co-authored 2 publications receiving 216 citations.
Topics: Gate array

Papers
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Patent
Sheng Feng1, Jung-Cheun Lien1, Eddy C. Huang1, Chung-yuan Sun1, Tong Liu1, Naihui Liao1, Weidong Xiong1 
31 Jan 2002
TL;DR: In this paper, a plurality of FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals.
Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

210 citations

Patent
Tong Liu1, Jung-Cheun Lien1, Sheng Feng1, Eddy C. Huang1, Chung-yuan Sun1, Naihui Liao1, Weidong Xiong1 
15 Feb 2002
TL;DR: A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array is described in this article. But the freeway system has a first set of routing conductors configured to transfer signals between the input ports of interfaces in a first tile of the field PGA array and the output ports in interfaces in other tiles in the field PPGA array.
Abstract: A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.

6 citations


Cited by
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Patent
05 Oct 2001
TL;DR: In this article, a customizable logic array including an array of programmable cells having a multiplicity of inputs and amultiplicity of outputs and customized interconnections providing permanent direct interconnection among at least a plurality of the multiplicity inputs and at least the plurality of outputs was described.
Abstract: This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

425 citations

Patent
19 Aug 2010
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

417 citations

Patent
28 Jun 2011
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

413 citations

Patent
28 Mar 2011
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

351 citations

Patent
10 Mar 2004
TL;DR: In this article, a programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed, where the transistor has its gate formed from the column bitlines and its source connected to the row wordlines.
Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed p+ region to form a p-n diode in the substrate underlying the gate of the transistor. Further, the wordline is formed from a buried diffusion N+ layer while the column bitline is formed from a counterdoped polysilicon layer.

225 citations