Weike Wang

Bio: Weike Wang is an academic researcher from MaxLinear. The author has contributed to research in topics: Intermodulation. The author has an hindex of 1, co-authored 1 publications receiving 6 citations.

Intermodulation Linearity Characteristics of 14-nm RF FinFETs

Abstract: This paper investigates the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series. Linearity sweet spots with respect to gate voltage and RF power, as well as its drain voltage dependence, are examined. Key BSIM-CMG model parameters required for simultaneous fitting of dc I–V , S-parameters, and intermodulation distortion are identified and demonstrated. Volterra series analysis shows that distortion resulting from ${V}_{\textsf {DS}}$ derivatives of ${I}_{\textsf {DS}}$ dominates at most biases. A minimum third-order intercept gate voltage ${V}_{\textsf {GS,IP3}}$ of 0.5 V is observed, compared with 0.7 V in a 28-nm high- ${k}$ metal-gate planar device.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

Gate Oxide Variability Analysis of a Novel 3 nm Truncated Fin–FinFET for High Circuitry Performance

Abstract: In this work, we examined the analog and circuitry amplifying capacity of our novel 3 nm Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at this small scale of gate length. Both oxide widths of high K-material HfO2 have their own individual benefits, due to high gate controllability as compared to conventional FinFETs having SiO2 as a gate oxide. The device works best with Tox = 1 nm in terms of power amplification. When tested with this width of gate oxide, we end up with increase of 59.18%, 7.22% and 12.11 times at corresponding peak values of Unilateral power gain (Gu), IP3 and fmax. This actually evident the enhanced performance of TF-FinFET for A.C applications at this high range of frequency of the input signal. When device tested at Tox = 1 nm, we end up with the increase of 45%, 21.45%, 16% and decrease of 65% at the corresponding peak values of Intrinsic delay (ti), Transconductance (gm), Drain current (ID) and OFF-state current (IOFF). These results of simulation also showed the compatibility of TF-FinFET in terms of high-performance analog application. After these analyses, we can expect a strong potential for wide variety of applications to high-speed System on chip from this device.

Benchmarking of Analog/RF Performance of Fin-FET, NW-FET, and NS-FET in the Ultimate Scaling Limit

Abstract: In this work, we examine and benchmark the analog/RF performance metrics of silicon-based multigate devices, such as Fin-FET, gate-all-around nanowire (NW)-FET, and gate-all-around nanosheet (NS)-FET, in the ultimate scaling limit of sub-5-nm technology node. The performance analysis of multigate devices is done using a fully calibrated 3-D technology computer-aided design (TCAD) simulation based on self-consistent solutions of Poisson’s equation, drift-diffusion transport equation, and carrier continuity equation with quantum correction terms for accounting band-to-band tunneling and confinement effects. Our performance benchmarking suggests that NS-FET with (100) surface orientation is a more favorable candidate over NW-FET and Fin-FET for analog/RF applications with higher voltage gain (32 V/V), higher peak cutoff frequency (373 GHz), and higher maximum oscillation frequency (389 GHz) at the 5-nm technology node. The performance benefits of NS-FET are found to be retained by decreasing the channel length, increasing the effective device width, and stacking the multichannel. Furthermore, our studies identify the proper directions to optimizations for achieving high-frequency and high-gain RF operations with multigate devices.