Wen-Shiang Liao

Bio: Wen-Shiang Liao is an academic researcher from Minghsin University of Science and Technology. The author has contributed to research in topics: MOSFET & Threshold voltage. The author has an hindex of 6, co-authored 39 publications receiving 140 citations. Previous affiliations of Wen-Shiang Liao include Hubei University & Wuhan University.

Investigation of Reliability Characteristics in NMOS and PMOS FinFETs

Abstract: Three-dimensional vertical double-gate (FinFET) devices with a high aspect ratio (Si-fin height/width = Hfin/Wfin = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness have been successfully fabricated. Reliability characterizations, including hot-carrier injection (HCI) for NMOS FinFETs and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out in order to determine their respective lifetimes. The predicted HCI dc lifetime for a 50-nm gate-length NMOS FinFET device at the normal operating voltage (Vcc) of 1.1 V is 133 years. A wider fin-width (27 nm) PMOS FinFET exhibits promising NBTI lifetime such as 26.84 years operating at Vcc = 1.1 V, whereas lifetime is degraded for a narrower fin-width (17 nm) device that yields 2.76 years of lifetime at the same operating voltage and stress conditions.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

Abstract: A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD- $\hbox{SiN}_{x}$ Stressing Layer

Abstract: In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been successfully fabricated. The performance improvements of devices with a gate length (Lg )of down to 40 nm were studied. For long-channel SiGe-channel PMOS, the mobility is at least 50% higher than that of the conventional bulk-Si PMOS. Moreover, compared to the conventional short-channel SiGe-channel devices, the highly compressive CESL stressor shows 32% current gain for Lg = 40 nm PMOS with the thinnest 9 A Si-cap. Therefore, integrating the stressed CESL technique into the SiGe-channel structure is an efficient method for improving PMOS device performance.

A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer

Abstract: Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 A nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. The drive current (ION), off current (IOFF), subthreshold swing (SS), drain-induced barrier lowering (DIBL) and transistor gate delay of 30 nm gate length (Lg) of FinFETs illustrate the promising device performance. The TCAD simulations demonstrate that both threshold voltage (Vth) and off current can be adjusted appropriately through the full silicidation (FUSI) of CoSi2 gate engineering. Moreover, the drive currents of n- and p-channel FinFETs are able to be further enhanced once applying the raised Source/Drain (S/D) approach technology for reducing the S/D resistance drastically.

LDMOS Transistor High-Frequency Performance Enhancements by Strain

Abstract: The effects of mechanical stress on the dc and high-frequency performances of laterally diffused MOS (LDMOS) transistors with different layout structures were investigated by using the wafer bending method. A 3.1% peak cutoff frequency (fT) enhancement is achieved for the multifinger device under 0.051% biaxial tensile strain. For LDMOS with annular layout, the fT enhancement is increased to 3.7% due to the various channel directions. Our results suggest the strain technology can be adopted in LDMOS for RF applications. The transconductance and gate capacitance were also extracted to clearly demonstrate the fT variations.

Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical Performance

Abstract: A new approach is presented aimed at modeling mechanical stress effects which impact MOSFET electrical behavior. It is successful in accounting for mobility variations experimentally evidenced on complex MOSFET geometries. The newly developed mobility model proves to be an efficient way to include mechanical stress effects into standard simulation models. We show that stress effects can and should be taken into account in the IC design phase in present and sub 90 nm nodes CMOS generations.

Fin-Last FinFET and Methods of Forming Same

Abstract: Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin.

The impact of thickness and thermal annealing on refractive index for aluminum oxide thin films deposited by atomic layer deposition

Abstract: The aluminum oxide (Al2O3) thin films with various thicknesses under 50 nm were deposited by atomic layer deposition (ALD) on silicon substrate. The surface topography investigated by atomic force microscopy (AFM) revealed that the samples were smooth and crack-free. The ellipsometric spectra of Al2O3 thin films were measured and analyzed before and after annealing in nitrogen condition in the wavelength range from 250 to 1,000 nm, respectively. The refractive index of Al2O3 thin films was described by Cauchy model and the ellipsometric spectra data were fitted to a five-medium model consisting of Si substrate/SiO2 layer/Al2O3 layer/surface roughness/air ambient structure. It is found that the refractive index of Al2O3 thin films decrease with increasing film thickness and the changing trend revised after annealing. The phenomenon is believed to arise from the mechanical stress in ALD-Al2O3 thin films. A thickness transition is also found by transmission electron microscopy (TEM) and SE after 900°C annealing.