Wenli Jiao

Bio: Wenli Jiao is an academic researcher from Harbin Engineering University. The author has contributed to research in topics: Power MOSFET & Electrode. The author has an hindex of 5, co-authored 12 publications receiving 81 citations.

Gate Enhanced Power UMOSFET With Ultralow On-Resistance

Abstract: Gate enhanced power UMOSFET (GE-UMOS) is proposed to decrease the specific on -resistance of the device. The key feature of this structure is that the deep trench polysilicon electrode is contacted to the gate electrode, maintaining the breakdown voltage and forming the high electron current density at side n-drift region, thus resulting in a lower on -resistance compared to the superjunction structure and gradient oxide-bypassed (GOB) structure. Furthermore, the performance of GE-UMOS is proved by comparing with the GOB-UMOS structure.

High-Performance Gate-Enhanced Power UMOSFET With Optimized Structure

Abstract: An optimized gate-enhanced (GE) power UMOSFET with split gate (SGE-UMOS) is proposed. This device shows the reduction in specific on-state resistance (Rsp) at a breakdown voltage of 119 V as compared to the gradient oxide-bypassed (GOB) UMOS and GE-UMOS devices, which is due to the higher N-type concentration in the drift region. In addition, the split-gate floating structure in SGE-UMOS also reduces the gate-source electrode parasitic capacitor. The numerical simulation results indicate that the proposed device features high performance with improved Rsp and Qg as compared to that of the GOB-UMOS and GE-UMOS devices.

Split-Gate-Enhanced UMOSFET With an Optimized Layout of Trench Surrounding Mesa

Abstract: An optimized split-gate-enhanced UMOSFET (SGE-UMOS) layout design is proposed, and its mechanism is investigated by 2-D and 3-D simulations. The layout features trench surrounding mesa (TSM): First, it optimizes the distribution of electric field density in the outer active mesa, reduces the electric-field crowding effect, and improves the breakdown voltage of the SGE-UMOS device. Second, it is unnecessary to design the layout corner with a large diameter in the termination region for the TSM structure as the conventional mesa surrounding trench (MST) structure, which is more efficient in terms of silicon usage. Rsp.on is reduced when compared with the MST structure within the same rectangular chip area. The BV of SGE-UMOS is increased from 72 to 115 V, and Rsp.on is reduced by approximately 3.5% as compared with the MST structure, due to the application of the TSM. Finally, it needs five masks in the process, and the trenches in active and termination regions are formed with the same processing steps; hence, the manufacturing process is simplified, and the cost is reduced as well.

Split-Gate-Enhanced Power UMOSFET With Soft Reverse Recovery

Abstract: A split-gate-enhanced power UMOSFET integrated with Schottky element is studied. In this device, a Schottky rectifier is integrated into every unit cell of the split-gate-enhanced UMOSFET (SGE-UMOS). 2-D simulations show that the device can achieve a low forward voltage drop of 0.48 V, around 28% lower than the 0.78 V of an SGE-UMOS. Numerical simulation also shows a 38% reduction in the reverse recovery time and three times improvement in the softness factor at a breakdown voltage (BV) of 150 V when compared with SGE-UMOS at room temperature. By reducing the width of the Schottky rectifier electrode, a further reduction in the leakage current until approaching the SGE-UMOS can be obtained. The unclamped inductive switching and the reverse recovery characteristics at an elevated temperature of 400 K, and the ON-state and OFF-state BV versus temperature are also studied.

Terminal structure of splitting gate groove power modular operating system (MOS) device and manufacturing method thereof

Abstract: The invention provides a terminal structure of a splitting gate groove power modular operating system (MOS) device and a manufacturing method thereof. The terminal structure comprises a grid leading-out electrode (101), a grid electrode lower part suspended polycrystalline silicon electrode (102), a thick oxidized layer (103), grid electrode connecting metal (104), a source electrode (105), a floating area (N-) (106) and a drain electrode (107); and the grid electrode leading-out electrode (101), the grid electrode lower part suspended polycrystalline silicon electrode (102) and the thick oxidized layer (103) are assembled to form the device terminal and are formed through a same mask plate and same technique. The splitting gate groove power MOS device structure is realized through a process manufacturing flow of five photoetching plates, so the breakdown voltage and parasitic capacitance of the device are not influenced, while ultralow conducting resistance of the device can be guaranteed; and the production cost of the device can be reduced, while the process manufacturing flow is optimized.

Power Semiconductor Devices

Abstract: Power semiconductor devices constitute the heart of modern power electronic apparatus. They are used in power electronic converters in the form of a matrix of on-off switches, and help to convert power from ac-to-dc (rectifier), dc-to-dc (chopper), dc-to-ac (inverter), and ac-to-ac at the same (ac controller) or different frequencies (cycloconverter). The switching mode power conversion gives high efficiency, but the disadvantage is that due to the nonlinearity of switches, harmonics are generated at both the supply and load sides. The switches are not ideal, and they have conduction and turn-on and turn-off switching losses. Converters are widely used in applications such as heating and lighting controls, ac and dc power supplies, electrochemical processes, dc and ac motor drives, static VAR generation, active harmonic filtering, etc. Although the cost of power semiconductor devices in power electronic equipment may hardly exceed 20–30 percent, the total equipment cost and performance may be highly influenced by the characteristics of the devices. An engineer designing equipment must understand the devices and their characteristics thoroughly in order to design efficient, reliable, and cost-effective systems with optimum performance. It is interesting to note that the modern technology evolution in power electronics has generally followed the evolution of power semiconductor devices. The advancement of microelectronics has greatly contributed to the knowledge of power device materials, processing, fabrication, packaging, modeling, and simulation. Today’s power semiconductor devices are almost exclusively based on silicon material and can be classified as follows:

100 V class multiple stepped oxide field plate trench MOSFET (MSO-FP-MOSFET) aimed to ultimate structure realization

Abstract: For low-voltage power MOSFETs technology, Field Plate (FP) and Superjunction (SJ) structures have been applied to reduce on-resistance drastically. As one of the approach for the ultimate structure realization, we propose a multiple stepped oxide FP-MOSFET (MSO-FP-MOSFET) that is extremely close to ideal gradient oxide structure. We have validated an optimum device structure by TCAD simulation and achieved lowest on-resistance of 28.5 mΩmm2 at breakdown voltage of 115.2 V. This performance indicates 25 % improvement compared to conventional devices. Moreover, to demonstrate the MSO-FP-MOSFET characteristics for the first time, we present some measurement data of TEG samples.

An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss

Abstract: In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage ( ${V}_{\textsf {BR}}$ ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time ( ${T}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off time ( ${T}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss ( ${E}_{\mathbf {SW}}$ ).

Simulation Study of 4H-SiC UMOSFET Structure With p + -polySi/SiC Shielded Region

Abstract: In this paper, we propose an enhanced efficiency 4H-SiC U-shaped trench-gate MOSFET (UMOSFET) structure. The proposed device structure takes an advantage of a p+-polySi/SiC shielded region to reduce the on-state specific resistance. We show that the heterojunction diode formed by the p+-polySi and the n-drift regions improves the body diode effect, and thereby, reduces the reverse recovery charge. Further, we illustrate through simulation results that in comparison with the traditional p+-SiC shielded UMOSFET, the proposed device structure provides a 56.5% improvement in the figure of merit (including the breakdown voltage and on-resistance), and a 35.7% and 55.5% reduction in specific on-resistance and reverse recovery charge, respectively.

A Review of Superjunction Vertical Diffused MOSFET

Abstract: Superjunction has arguably been the most creative and important concept in power device field Superjunction vertical diffused MOSFET (SJ VDMOS) has been commercialized and the research effort to l