Werner Pamler

Bio: Werner Pamler is an academic researcher from Infineon Technologies. The author has contributed to research in topics: Layer (electronics) & Substrate (printing). The author has an hindex of 10, co-authored 58 publications receiving 857 citations. Previous affiliations of Werner Pamler include Technische Universität München & Siemens.

Silicon-Nanowire Transistors with Intruded Nickel-Silicide Contacts

Abstract: Schottky barrier field effect transistors based on individual catalytically-grown and undoped Si-nanowires (NW) have been fabricated and characterized with respect to their gate lengths. The gate length was shortened by the axial, self-aligned formation of nickel-silicide source and drain segments along the NW. The transistors with 10−30 nm NW diameters displayed p-type behaviour, sustained current densities of up to 0.5 MA/cm2, and exhibited on/off current ratios of up to 107. The on-currents were limited and kept constant by the Schottky contacts for gate lengths below 1 μm, and decreased exponentially for gate lengths exceeding 1 μm.

How do carbon nanotubes fit into the semiconductor roadmap

Abstract: This paper presents an overview of the issues related to the integration of carbon nanotubes into microelectronics systems. Particular emphasis is placed on the use of carbon nanotubes as on-chip wiring (interconnects) and active devices (transistors), the two main building blocks of current semiconductor circuits. The properties of state-of-the art devices are compared in order to test the viability of replacing silicon-based components with carbon nanotubes. Further, the problems associated with the construction of nanotube-based devices are discussed.

Carbon Nanotubes for Microelectronics

Abstract: Despite all prophecies of its end, silicon-based microelectronics still follows Moore's Law and continues to develop rapidly. However, the inherent physical limits will eventually be reached. Carbon nanotubes offer the potential for further miniaturization as long as it is possible to selectively deposit them with defined properties.

Application of auger ewlectron depth profile analysis to thin film interdiffusion studies

Abstract: Because of its good depth resolution, the Auger electron depth profile analysis allows to investigate diffusion phenomena in thin films directly. Complicated calibration procedures, however, are needed to correct for the matrix effects inherent in the Auger method, particularly artefacts due to the sputtering process. In this paper, two types of thin-film systems are presented in order to determine diffusion coefficients from depth profiles: double-layer and periodic multi-layer film structures. Compared to the double-layer films, the multi-layer structure has the advantage of less stringent requirements on depth resolution and allows to detect smaller diffusion effects. Finally, it is shown how grain boundary and bulk diffusion data can be extracted separately from the composition profiles.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Three dimensional structure memory

Abstract: A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Ultrathin Films of Single-Walled Carbon Nanotubes for Electronics and Sensors: A Review of Fundamental and Applied Aspects

Abstract: Ultrathin films of single-walled carbon nanotubes (SWNTs) represent an attractive, emerging class of material, with properties that can approach the exceptional electrical, mechanical, and optical characteristics of individual SWNTs, in a format that, unlike isolated tubes, is readily suitable for scalable integration into devices. These features suggest the potential for realistic applications as conducting or semiconducting layers in diverse types of electronic, optoelectronic and sensor systems. This article reviews recent advances in assembly techniques for forming such films, modeling and experimental work that reveals their collective properties, and engineering aspects of implementation in sensors and in electronic devices and circuits with various levels of complexity. A concluding discussion provides some perspectives on possibilities for future work in fundamental and applied aspects.

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

Silicon quantum electronics

Abstract: This review describes recent groundbreaking results in Si, Si/SiGe, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the physical understanding of quantum effects in silicon. Recent critical steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.