Analog-to-digital converters (ADCs) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADCs, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Gs/s), resolution appears to be limited by thermal noise. At sampling rates ranging from /spl sim/2 Ms/s to /spl sim/4 giga samples per second (Gs/s), resolution falls off by /spl sim/1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADCs operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The trend toward single-chip ADCs brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only /spl sim/1.5 bits for any given sampling frequency over the last six-eight years.

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Analog-to-digital converter survey and analysis

Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

/pdf/understanding-delta-sigma-data-converters-1lhwu28dym.pdf

Understanding Delta-Sigma Data Converters

The most exciting development in parallel computer architecture is the convergence of traditionally disparate approaches on a common machine structure. This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures. It then examines the design issues that are critical to all parallel architecture across the full range of modern design, covering data access, communication performance, coordination of cooperative work, and correct implementation of useful semantics. It not only describes the hardware and software techniques for addressing each of these issues but also explores how these techniques interact in the same system. Examining architecture from an application-driven perspective, it provides comprehensive discussions of parallel programming for high performance and of workload-driven evaluation, based on understanding hardware-software interactions.


* synthesizes a decade of research and development for practicing engineers, graduate students, and researchers in parallel computer architecture, system software, and applications development

* presents in-depth application case studies from computer graphics, computational science and engineering, and data mining to demonstrate sound quantitative evaluation of design trade-offs 

* describes the process of programming for performance, including both the architecture-independent and architecture-dependent aspects, with examples and case-studies

* illustrates bus-based and network-based parallel systems with case studies of more than a dozen important commercial designs

Table of Contents

1 Introduction 
2 Parallel Programs 
3 Programming for Performance 
4 Workload-Driven Evaluation 
5 Shared Memory Multiprocessors 
6 Snoop-based Multiprocessor Design 
7 Scalable Multiprocessors
8 Directory-based Cache Coherence
9 Hardware-Software Tradeoffs 
10 Interconnection Network Design 
11 Latency Tolerance 
12 Future Directions 
APPENDIX A Parallel Benchmark Suites

Parallel Computer Architecture: A Hardware/Software Approach

From the Publisher:
This is undoubtedly the most accessible book on digital signal processing (DSP) available to the beginner. Using intuitive explanations and well-chosen examples, this book gives you the tools to develop a fundamental understanding of DSP theory. The author covers the essential mathematics by explaining the meaning and significance of the key DSP equations. Comprehensive in scope, and gentle in approach, the book will help you achieve a thorough grasp of the basics and move gradually to more sophisticated DSP concepts and applications.

/pdf/understanding-digital-signal-processing-1tunqv7j3t.pdf

Understanding digital signal processing

Guided by brain-like ‘spiking’ computational frameworks, neuromorphic computing—brain-inspired computing for machine intelligence—promises to realize artificial intelligence while reducing the energy requirements of computing platforms. This interdisciplinary field began with the implementation of silicon circuits for biological neural routines, but has evolved to encompass the hardware implementation of algorithms with spike-based encoding and event-driven representations. Here we provide an overview of the developments in neuromorphic computing for both algorithms and hardware and highlight the fundamentals of learning and hardware frameworks. We discuss the main challenges and the future prospects of neuromorphic computing, with emphasis on algorithm–hardware codesign. The authors review the advantages and future prospects of neuromorphic computing, a multidisciplinary engineering concept for energy-efficient artificial intelligence with brain-inspired functionality.

Towards spike-based machine intelligence with neuromorphic computing.

Continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffer from a problem not seen in discrete-time (DT) designs, that of excess loop delay: nonzero delay between the quantizer clock edge and the time when a change in output bit is seen at the feedback point in the modulator. This paper analytically shows how such delay affects the equivalence between the CT modulator loop filter and its DT counterpart. The effect of this delay on modulator dynamic range is studied through simulation for the standard double-integration (low pass) CT modulator and its equivalent fourth-order f/sub s//4 band pass circuit. For the first time, the results are extended to higher order low-pass and bandpass designs, as well as multibit designs. Methods for alleviating the performance loss caused by excess loop delay are also discussed.

Excess loop delay in continuous-time delta-sigma modulators

The performance of continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT /spl Delta//spl Sigma/M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT /spl Delta//spl Sigma/M given jitter and metastability constraints.

Clock jitter and quantizer metastability in continuous-time delta-sigma modulators

A radio frequency power amplifier includes a feedback control system coupled to an input signal and a first feedback signal and configured to provide an output; a controlled supply configured to provide power that is controlled in accordance with a signal; and a radio frequency gain stage powered from the controlled supply, driven by the output from the feedback control system, and configured to provide an output signal at the radio frequency to a resonant load, where the first feedback signal corresponds to the output signal. Some embodiments include a sequencer in the feedback control system and others utilize an additional feedback loop to control the power provided by the controlled supply.

Radio frequency power amplifier and method using a controlled supply

Computational RAM is a processor-in-memory architecture that makes highly effective use of internal memory bandwidth by pitch-matching simple processing elements to memory columns Computational RAM can function either as a conventional memory chip or as a SIMD (single-instruction stream, multiple-data stream) computer When used as a memory, computational RAM is competitive with conventional DRAM in terms of access time, packaging and cost Adding logic to memory is not a simple question of bolting together two existing designs The paper considers how computational RAM integrates processing power with memory by using an architecture that preserves and exploits the features of memory

Computational RAM: implementing processors in memory

This paper investigates and resolves in-phase/quadrature phase (I/Q) imbalances between the input paths of quadrature IF receivers. These mismatches along the paths result in the image interference aliasing into the desired signal band, thus reducing the dynamic range and degrading the performance of the receivers. I/Q errors occur because of gain and phase imbalances between quadrature mixers. They are also caused by capacitor mismatches in analog-to-digital converters (A/Ds), which are designed to be identical for each input path. This paper presents a novel and feasible digital signal processing (DSP) solution for the I/Q mismatch problems. The system includes a novel complex least mean square algorithm and a modified adaptive noise canceler (signal separator) to separate the desired signal and the image noise caused by the mismatch. The noise canceler can also solve the signal leakage problem, which is that the noise reference includes signal components. This system was implemented in a Xilinx FPGA and an Analog Devices DSP chip. It was tested with a complex intermediate frequency receiver, which includes an analog front end and a complex sigma-delta modulator. Both simulation results and test results show a dramatic attenuation of the image noise. Extending applications of the system to N-path systems further indicates the robustness and feasibility of this novel adaptive mismatch cancellation system.

William Martin Snelgrove

Papers

Excess loop delay in continuous-time delta-sigma modulators

Clock jitter and quantizer metastability in continuous-time delta-sigma modulators

Radio frequency power amplifier and method using a controlled supply

Computational RAM: implementing processors in memory

A novel adaptive mismatch cancellation system for quadrature IF radio receivers