Woojin Rim

Bio: Woojin Rim is an academic researcher from Samsung. The author has contributed to research in topics: Memory cell & Sense amplifier. The author has an hindex of 8, co-authored 25 publications receiving 413 citations. Previous affiliations of Woojin Rim include SK Hynix & Korea University.

13.2 A 14nm FinFET 128Mb 6T SRAM with V MIN -enhancement techniques for low-power applications

Abstract: With the explosive growth of battery-operated portable devices, the demand for low power and small size has been increasing for system-on-a-chip (SoC). The FinFET is considered as one of the most promising technologies for future low-power mobile applications because of its good scaling ability, high on-current, better SCE and subthreshold slope, and small leakage current [1]. As a key approach for low-power, supply-voltage (VDD) scaling has been widely used in SoC design. However, SRAM is the limiting factor of voltage-scaling, since all SRAM functions of read, write, and hold-stability are highly influenced by increased variations at low VDD, resulting in lower yield. In addition, the width-quantization property of FinFET device reduces the design window for transistor sizing, and increases the failure probability due to the un-optimized bitcell sizing [1]. In order to overcome the bitcell challenges to high yield, peripheral-assist techniques are required. In this paper, we present 14nm FinFET-based 128Mb 6T SRAM chips featuring low-VMIN with newly developed assist techniques.

A Highly Sensitive Capacitive Touch Sensor Integrated on a Thin-Film-Encapsulated Active-Matrix OLED for Ultrathin Displays

Abstract: This paper presents ultrathin and highly sensitive input/output devices consisting of a capacitive touch sensor (Cap-TSP) integrated on thin-film-encapsulated active-matrix organic light-emitting diodes (OLEDs). The optimal structure of the electrically noise-free capacitive touch sensor, which is assembled on a thin-film-encapsulated active-matrix OLED (AMOLED) display, is obtained by investigating the internal electrical field distribution and capacitance change based on the Q3D Extractor model. Electrostatic simulations have verified malfunction-free electrical signals for 4-in diagonal-sized capacitive touch sensors on AMOLEDs possessing a 100-μm-thick optically clear adhesive (OCA, er = 1.4) layer. The prototype OLED platform using the capacitive touch sensors exhibits an overall thickness of 1.2 mm, which is the lowest thickness for commercially available OLED platforms.

A 14 nm FinFET 128 Mb SRAM With V $_{\rm MIN}$ Enhancement Techniques for Low-Power Applications

Abstract: Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 $\mu$ m $^{2}$ and a 0.080 $\mu$ m $^{2}$ 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve ${\rm V}_{{\rm MIN}}$ of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the ${\rm V}_{{\rm MIN}}$ of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 ${\rm V}_{{\rm MIN}}$ with 200 mV improvement by NBL, and 0.47 ${\rm V}_{{\rm MIN}}$ for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved ${\rm V}_{{\rm MIN}}$ reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

Abstract: Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology A 0040 $\mu \text{m}^{2}$ 6T SRAM bitcell is designed for high density (HD), and 0049 $\mu \text{m}^{2}$ for high performance (HP) The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage ( $V_{\mathrm{ MIN}}$ ) and assist overheads The dual-transient wordline scheme is proposed to improve the $V_{\mathrm{ MIN}}$ by 475 mV for the 128 Mb 6T-HP SRAM The suppressed bitline scheme with negative bitline improves the $V_{\mathrm{ MIN}}$ by 135 mV for the 128 Mb 6T-HD SRAM The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications

Abstract: SRAM plays an integral role in the power, performance, and area of a mobile system-on-a-chip. To achieve low power and high density, extreme ultraviolet (EUV) technology is adopted for the 7nm FinFET technology [3-4]. Conventional ArF immersion with a single exposure for an extreme high-resolution patterning shows the limitation of lithographic patterning. Therefore, multi-patterning lithographic technique is applied to support a high-resolution lithography. However, this also includes process variations due to using multi-pattering masks. Alternatively, EUV offers competitive scaling with a single-mask with the benefit of smaller wavelength, which provides smaller process variation with less additional pattering. Figure 11.2.1 shows a 7nm EUV FinFET 6T high-density (HD) SRAM bitcell with an area of 0.026μσι2. The pull-up, pass-gate, and pull-down ratios are 1:1:1 for high-density and low-power applications. Another benefit of EUV technology also features a bi-directional metal layer with a scaled pitch that provides an extra degree of freedom for signal and power routing. Figure 11.2.2 highlights EUV benefits in accordance with bi-directional metals. A uni-directional metal layer requires different metal layer to connect two nets, and have no choice but to support the limited via between two perpendicular metal lines with the limited metal width. A wider metal allows placement of more vias between the metal lines, but it does not demonstrate optimum Power, Performance, and Area (PPA) with redundant parasitic capacitance. However, EUV provides bi-directional metal lines, where the different layers of metal are coherent in the same direction. Therefore, more vias can be placed to reduce the IR-drop with smaller parasitic capacitance and resistance. Figure 11.2.2 illustrates the delay impact versus stacked-via distance in a standard cell array. It shows that the timing penalty is directly proportional to the stacked via distance in a uni-directional metal routing.

Single layer capacitive imaging sensors

Abstract: Embodiments of the invention generally provide an input device that includes a plurality of sensing elements that are interconnected in desired way to acquire positional information of an input object, so that the acquired positional information can be used by other system components to control a display or other useful system components. One or more of the embodiments described herein, utilizes one or more of the techniques and sensor electrode array configuration disclosed herein to reduce or minimize the number of traces and/or electrodes required to sense the position of an input object within a sensing region of the input device.

Conductive Elastomers with Autonomic Self-Healing Properties

Abstract: Healable, electrically conductive materials are highly desirable and valuable for the development of various modern electronics. But the preparation of a material combining good mechanical elasticity, functional properties, and intrinsic self-healing ability remains a great challenge. Here, we design composites by connecting a polymer network and single-walled carbon nanotubes (SWCNTs) through host-guest interactions. The resulting materials show bulk electrical conductivity, proximity sensitivity, humidity sensitivity and are able to self-heal without external stimulus under ambient conditions rapidly. Furthermore, they also possess elasticity comparable to commercial rubbers.

High Dielectric Performances of Flexible and Transparent Cellulose Hybrid Films Controlled by Multidimensional Metal Nanostructures

Abstract: Various wearable electronic devices have been developed for extensive outdoor activities. The key metrics for these wearable devices are high touch sensitivity and good mechanical and thermal stability of the flexible touchscreen panels (TSPs). Their dielectric constants (k) are important for high touch sensitivities. Thus, studies on flexible and transparent cover layers that have high k with outstanding mechanical and thermal reliabilities are essential. Herein, an unconventional approach for forming flexible and transparent cellulose nanofiber (CNF) films is reported. These films are used to embed ultralong metal nanofibers that serve as nanofillers to increase k significantly (above 9.2 with high transmittance of 90%). Also, by controlling the dimensions and aspect ratios of these fillers, the effects of their nanostructures and contents on the optical and dielectric properties of the films have been studied. The length of the nanofibers can be controlled using a stretching method to break the highly aligned, ultralong nanofibers. These nanofiber-embedded, high-k films are mechanically and thermally stable, and they have better Young's modulus and tensile strength with lower thermal expansion than commercial transparent plastics. The demonstration of highly sensitive TSPs using high-k CNF film for smartphones suggests that this film has significant potential for next-generation, portable electronic devices.

RIO: A Pervasive RFID-based Touch Gesture Interface

Abstract: In this paper, we design and develop RIO, a novel battery-free touch sensing user interface (UI) primitive for future IoT and smart spaces. RIO enables UIs to be constructed using off-the-shelf RFID readers and tags, and provides a unique approach to designing smart IoT spaces. With RIO, any surface can be turned into a touch-aware surface by simply attaching RFID tags to them. RIO also supports custom-designed RFID tags, and thus allows specially customized UIs to be easily deployed into a real-world environment. RIO is built using the technique of impedance tracking: when a human finger touches the surface of an RFID tag, the impedance of the antenna changes. This change manifests as a change in the phase of the RFID backscattered signal, and is used by RIO to track fine-grained touch movement over both off-the shelf and custom built tags. We study this impedance behavior in-depth and show how RIO is a reliable UI primitive that is robust even within a multi-tag environment. We leverage this primitive to build a prototype of RIO that can continuously locate a finger during a swipe movement to within 3 mm of its actual position. We also show how custom-design RFID tags can be built and used with RIO, and provide two example applications that demonstrate its real-world use.

Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

Abstract: Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in hardware accelerator design for deep learning. The input vector and weight matrix multiplication, i.e., the multiply-and-accumulate (MAC) operation, could be performed in the analog domain within memory sub-array, leading to significant improvements in throughput and energy efficiency. Static random access memory (SRAM) and emerging non-volatile memories such as resistive random access memory (RRAM) are promising candidates to store the weights of deep neural network (DNN) models. In this review, firstly we survey the recent progresses in SRAM and RRAM based CIM macros that have been demonstrated in silicon. Then we discuss general design challenges of the CIM chips including analog-to-digital conversion (ADC) bottleneck, variations in analog compute, and device non-idealities. Next we introduce the DNN+NeuroSim benchmark framework that is capable of evaluating versatile device technologies for CIM inference and training performance from software/hardware co-design's perspective.