Xi Qu

Bio: Xi Qu is an academic researcher from University of Electronic Science and Technology of China. The author has contributed to research in topics: Low-dropout regulator & Slew rate. The author has an hindex of 5, co-authored 11 publications receiving 117 citations.

An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

Abstract: An output capacitor-free low-dropout regulator (LDO) using a class-AB operational amplifier and an assistant push–pull output stage (APPOS) circuit to enable fast-transient response with ultralow-power dissipation is presented in this brief. The APPOS circuit is proposed to deliver an extra current that is directly proportional to the output current of the class-AB operational amplifier during transient state with an automatic on/off feature. Moreover, the small-signal and large-signal responses of LDO can be separately optimized. As a result, transient performances of LDO are improved significantly without requiring an area-consuming on-chip capacitor anymore. The proposed LDO has been implemented in a standard 0.35- $\mu\hbox{m}$ CMOS process. Experimental results show that the LDO can regulate the output voltage at 1.0 V from a 1.2-V supply voltage for the maximum load current of 100 mA. The output voltage fully recovers within 2.7 $\mu\hbox{s}$ with the load current switching from 100 $\mu\hbox{A}$ to 100 mA at a 1.2- $\mu\hbox{A}$ quiescent current.

A Resistorless CMOS Voltage Reference Based on Mutual Compensation of $V_{T}$ and $V_{\rm TH}$

Abstract: A novel temperature-stable nonbandgap voltage reference without resistors is presented in this brief, which is compatible with standard digital CMOS technology. Two linear-temperature terms, i.e., thermal voltage VT and threshold voltage VTH, are utilized to realize a low-temperature-dependent voltage reference with a significant reduction of nonlinear temperature terms. A self-biased threshold-voltage extractor circuit without any resistor is used to obtain the VTH and bias currents of the whole circuit. Based on ratioed transistors biased in a strong inversion region and the inverse-function technique, a temperature-insensitive gain can be applied to the proportional-to-absolute temperature term in the reference, and a weighted sum of VT and VTH is achieved. Experimental results of the proposed voltage reference implemented with a 0.35- μm CMOS process demonstrate that the output of voltage reference is 905.5 mV, a temperature coefficient of 14.8 ppm/°C with a temperature range of 0°C-100 °C is obtained at a 3.3-V power supply, and a power-supply noise attenuation of 61 dB is achieved without any filtering capacitor while dissipating a maximum supply current of 65 μA. The active area is 100 μm ×100 μm.

Ultralow-power fast-transient output-capacitor-less low-dropout regulator with advanced adaptive biasing circuit

Abstract: An ultra-low-power fast-transient output-capacitor-less low-dropout regulator (LDO) with advanced adaptive biasing (AAB) circuit is presented in this study. At light load, the AAB circuit only delivers 0.1 μA bias current to the amplifier to maintain the stability and reduce the quiescent current. At medium load to heavy load, the AAB circuit increases bias current to 2.5 μA for performance enhancement. A simple but effective hysteresis current comparator is proposed to eliminate the metastable region between the bias current transitions. When output voltage recovers from overshoot, the settling time at minimum load current of 1 μA is too long because of the 100-pF load capacitor. Hence, a gradually descending load current is delivered by AAB circuit for regulating output voltage from overshoot to the nominal value promptly. The proposed circuit has been implemented in a mixed-signal 0.13-μm CMOS process. From the measurement results, the proposed LDO regulates the output voltage at 0.8 V from a 1-V input with 2.9 μA quiescent current at minimum load. Output voltage could be fully recovered within 1.7 μs at a voltage spike <;120 mV where load current switches from 1 μA to 100 mA in 800 ns.

A fully on-chip 1-μW capacitor-free low-dropout regulator with adaptive output stage

Abstract: A fully on-chip 1-μW fast-transient response capacitor-free low-dropout regulator (LDO) using adaptive output stage (AOS) is presented in this paper in standard 0.13-μm CMOS process. The AOS circuit is proposed to deliver extra four times of output current of the operational amplifier at medium to heavy load to extend the bandwidth of the LDO and enhance the slew rate at the gate of the power transistor. And the AOS circuit is shut off at light load to reduce the quiescent current and maintain the stability without requiring area-consuming on-chip capacitor. Meanwhile, the proposed AOS circuit introduces VOUT offset at medium to heavy load to counteract the VOUT drop, which is caused by ILOAD increase. Hence, transient performances of LDO and VOUT drop between light load and full load are improved significantly with 1.1-μA quiescent current at light load. From the post simulation results, the LDO regulates the output voltage at 0.7 V from a 0.9-V supply voltage with a 100-mA maximum load current. The undershoot, the overshoot and the recovery time of the proposed LDO with ILOAD switching from 50 μA to 100 mA in 1 μs are about 130 mV, 130 mV and 1.5 μs, respectively. And the VOUT drop between light load and full load reduces to 0.16 mV.

Embedded capacitor multiplier gain boosting compensation for large-capacitive-load three-stage amplifier with slew rate enhancement

Abstract: An embedded capacitor multiplier gain boosting compensation (ECMGBC) technique with slew rate enhancement circuit is presented in this paper for a three-stage amplifier. The ECMGBC technique pushes the non-dominant complex poles of the amplifier to high frequencies for gain-bandwidth product (GBW) extension under low quiescent current. In addition, the proposed slew rate enhancement circuit improves the transient responses of ECMGBC amplifier without any problem of oscillation. The ECMGBC amplifier has been designed and simulated in a 0.35-µm mixed signal CMOS process. From the post-simulation results, the amplifier driving a 1,000-pF capacitance achieves a 1-MHz GBW with a phase margin of 60° by consuming 13.5-µA quiescent current. The total compensation capacitance is only 1.2 pF. The transient responses are simulated when the amplifier is in unity-gain non-inverting configuration with a 0.6-V step input at a 2-V supply. The 1 % settling time is 1.1 µs for a 1,000-pF load capacitance. Compared with previously reported works, the ECMGBC amplifier achieves good figures of merit. Moreover, the ECMGBC amplifier obtains a very high ratio of load capacitance to total compensation capacitance.

A Nano-Watt MOS-Only Voltage Reference With High-Slope PTAT Voltage Generators

Abstract: This brief presents an MOS-only voltage reference circuit with high-slope proportional-to-absolute-temperature (PTAT) voltage generators for ultra-low-power applications. Biased by a nano-ampere current reference circuit, the PTAT voltage generator is realized by an asymmetrical differential cell with two additional cross-coupled nMOS/pMOS pairs, which enhance the slope of the PTAT voltage remarkably. As a result, only two cascaded PTAT stages are used to compensate the complementary-to-absolute-temperature voltage generated directly by a diode-connected nMOS in the current reference circuit. Therefore, much power and chip area can be saved. A trimming circuit is also adopted to compensate the process-related reference voltage variations. The experimental results of the proposed reference circuit fabricated in a 0.18- $ {\mu }$ m standard CMOS process demonstrate that the circuit could operate under a minimum supply voltage of 1 V, and generate a reference voltage of 756 mV with temperature coefficient of 74 and 49.6 ppm/°C under 1-V and 1.8-V power supply, respectively. The proposed circuit consumes only 23 nA under a 1-V power supply, and the active area is only 95 $ {\mu }\text{m}\,\, {\times } \,\, 170 ~{\mu }\text{m}$ .

Exploiting Voltage Regulators to Enhance Various Power Attack Countermeasures

Abstract: The security implications of on-chip voltage regulation on the effectiveness of various voltage/frequency scaling-based countermeasures such as random dynamic voltage and frequency scaling (RDVFS), random dynamic voltage scaling (RDVS), and aggressive voltage and frequency scaling (AVFS) are investigated. The side-channel leakage mechanisms of different on-chip voltage regulator topologies are mathematically analyzed and verified with circuit level simulations. Correlation coefficient between the input data and monitored power consumption of a cryptographic circuit is used as the security metric to compare the impact of different on-chip voltage regulators when implemented with the aforementioned countermeasures. As compared to a cryptographic circuit without countermeasure, the RDVFS technique implemented with an on-chip switched-capacitor voltage converter reduces the correlation coefficient over 80 percent and over 92 percent against differential and leakage power analysis attacks, respectively, through masking the leakage of the clock frequency and supply voltage information in the monitored power profile.

Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO With Transient and Stability Enhancement in 65-nm CMOS

Abstract: An output-capacitorless low-dropout regulator (OCL-LDO) using a dual-active feedback frequency compensation (DAFFC) scheme with both transient and stability enhancement has been presented in this paper. The DAFFC scheme consists of two parallel active feedback paths, which creates two pole-zero pairs to effectively enhance the stability and transient response for the proposed OCL-LDO. Compared to the conventional single-path active-feedback frequency compensation method, the proposed DAFFC technique has provided one more design freedom with one more active feedback loop deployed and has been proved to be capable of obtaining better compensation effects with the same capacitor budget. Besides, the induced extra ac currents by the two active feedback loops have also enhanced the transient response of the proposed OCL-LDO. To substantiate the proposed DAFFC, a telescopic cascode output stage for error amplifier, and two on-chip compensation capacitors (5 and 1 pF, respectively) are needed. The proposed OCL-LDO has been implemented in 65-nm CMOS technology and the active chip area is 0.0105 mm2. The output voltage is 0.8 V, and the minimum input voltage is 0.95 V at 100-mA loading current. The proposed OCL-LDO can work stably in a load range of 0 to 100 mA with 14-μA quiescent current.

Low-Power Fast-Transient Capacitor-Less LDO Regulator With High Slew-Rate Class-AB Amplifier

Abstract: This brief presents a low-power fast-transient capacitor-less low-dropout regulator (CL-LDO) for system-on-a-chip applications. A low-quiescent-current class-AB amplifier with embedded slew-rate enhancement (SRE) circuit is proposed to improve both current efficiency and load transient performance. As the SRE circuit is directly controlled by the amplifier, only a minimum hardware overhead is required. The proposed CL-LDO is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. It occupies an active area of 0.031 mm2 and consumes a quiescent current of $10.2~\mu \text{A}$ . It is capable of delivering a maximum load current of 100 mA at 1.0-V output from a 1.2-V power supply. The measured results show that a settling time of $0.22~\mu \text{s}$ is achieved for load steps from 1 mA to 100 mA (and vice versa) with an edge time of $0.1~\mu \text{s}$ .

Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM

Abstract: The performance of switching devices such as display driver ICs is degraded by large power supply noise at switching frequencies from a few hundreds of kilohertz to a few megahertz. In order to minimize the power supply noise, a low-dropout (LDO) regulator with higher power supply rejection (PSR) is essential. In this brief, a capless LDO regulator with a negative capacitance circuit and voltage damper is proposed for enhancing PSR and figure of merit (FOM), respectively, in switching devices. The proposed LDO regulator is fabricated in a $0.18~\boldsymbol {\mu }\text{m}$ CMOS. Measurement results show that the proposed LDO regulator achieves −76 dB PSR at 1 MHz and 96.3 fs FOM with a total on-chip capacitance of as small as 12.7 pF.