Xiang Li

Bio: Xiang Li is an academic researcher from Shanghai Jiao Tong University. The author has contributed to research in topics: Layer (electronics) & Silicon. The author has an hindex of 6, co-authored 10 publications receiving 124 citations. Previous affiliations of Xiang Li include Agency for Science, Technology and Research & University of California, Santa Barbara.

On-chip intercalated-graphene inductors for next-generation radio frequency electronics

Abstract: On-chip metal inductors that revolutionized radio frequency electronics in the 1990s suffer from an inherent limitation in their scalability in state-of-the-art radio frequency integrated circuits. This is because the inductance density values for conventional metal inductors, which result from magnetic inductance alone, are limited by the laws of electromagnetic induction. Here, we report inductors made of intercalated graphene that uniquely exploit the relatively large kinetic inductance and high conductivity of the material to achieve both small form-factors and high inductance values, a combination that has proved difficult to attain so far. Our two-turn spiral inductors based on bromine-intercalated multilayer graphene exhibit a 1.5-fold higher inductance density, leading to a one-third area reduction, compared to conventional inductors, while providing undiminished Q-factors of up to 12. This purely material-enabled technique provides an attractive solution to the longstanding scaling problem of on-chip inductors and opens an unconventional path for the development of ultra-compact wireless communication systems.

Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire

Abstract: For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low leakage, tunability in drain current, as well as “AND” gate functionality with 50% reduction in area for both n- and p-type MOSFETs. The twin-gate device structure is also promising for implementing other device types such as stacked SONOS memory and tunneling FET. We anticipate that our vertically integrated device architecture will provide unique opportunities for realizing ultra-dense CMOS logic on a single nanowire.

Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect

Abstract: Graphene is very attractive for densely integrated and flexible high-frequency/RF IC applications due to its extraordinary electrical, thermal, and mechanical properties. This work presents the design, fabrication, and characterization of graphene on-chip inductors. The skin effect in graphene inductors is investigated experimentally for the first time based on a circuit model proposed and fitted from fabricated ¾-, 2-, and 3-turn spiral inductors. The operation frequencies are in 40–60 GHz range and Q-factors are around 3. Design and fabrication optimizations are performed to guide future studies.

HfO2 Based Resistive Switching Non-Volatile Memory (RRAM) and Its Potential for Embedded Applications

Abstract: In this letter, HfO2 based RRAM with varying device sizes are discussed with an analysis on their electrical characteristics. Device sizes of 60nm and 120nm were achieved by using different thickness of nitride spacer after 200nm contact hole is formed. Platinum (Pt) bottom electrode and Titanium Nitride (TiN) top electrode were used with HfO2 dielectric as the resistance switching layer. Uniform bipolar switching characteristics with a low Ireset of about 100µA are achieved with self-compliance effect. It is demonstrated that RRAM has a potential to be used as the embedded memory fabricated directly at the backend of CMOS process.

Surround gate CMOS semiconductor device

Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

Nanowire Electronics: From Nanoscale to Macroscale

Abstract: Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

A Megatrend Challenging Analytical Chemistry: Biosensor and Chemosensor Concepts Ready for the Internet of Things.

Abstract: The Internet of Things (IoT) is a megatrend that cuts across all scientific and engineering disciplines and establishes an integrating technical evolution to improve production efficiencies and daily human life. Linked machines and sensors use decision-making routines to work toward a common product or solution. Expanding this technical revolution into the value chain of complex areas such as agriculture, food production, and healthcare requires the implementation and connection of sophisticated (bio)analytical methods. Today, wearable sensors, monitors, and point-of-care diagnostic tests are part of our daily lives and improve patients' medical progression or athletes' monitoring capabilities that are already beyond imagination. Also, early contributions toward sensor networks and finally the IT revolution with wireless data collection and transmission via Bluetooth or smartphones have set the foundation to connect remote sensors and distributed analytical chemical services with centralized laboratories, cloud storage, and cloud computing. Here, we critically review those biosensor and chemosensor technologies and concepts used in an IoT setting or considered IoT-ready that were published in the period 2013-2018, while also pointing to those foundational concepts and ideas that arose over the last two decades. We focus on these sensors due to their unique ability to be remotely stationed and that easily function in networks and have made the greatest progress toward IoT integration. Finally, we highlight requirements and existing and future challenges and provide possible solutions important toward the vision of a seamless integration into a global analytical concept, which includes many more analytical techniques than sensors and includes foremost next-generation sequencing and separation principles coupled with MS detection.

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Abstract: We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.