Xiaodong Jin

Bio: Xiaodong Jin is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: CMOS & MOSFET. The author has an hindex of 6, co-authored 9 publications receiving 621 citations. Previous affiliations of Xiaodong Jin include University of California.

BSIM4 gate leakage model including source-drain partition

Abstract: Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed This model has been implemented in BSIM4

An effective gate resistance model for CMOS RF and noise modeling

Abstract: A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices. The accuracy of the model is validated with 2D simulations and experimental data. In addition, the effect of the gate resistance on the device noise behavior has been studied with measured data. The result shows that an accurate gate resistance model is essential for the noise modeling.

CMOS RF modeling for GHz communication IC's

Abstract: With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process. A major barrier to the realization of robust commercial CMOS RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies. The conventional microwave table-lookup-based approach requires a large database obtained from numerous device measurements and computationally intense simulations for accurate results. This method becomes prohibitively complex when used to simulate highly integrated CMOS communication systems; hence, a compact model, valid for a broad range of bias conditions and operating frequencies is desirable. BSIM3v3 has been widely accepted as a standard CMOS model for low frequency applications. Recent work has demonstrated the capability of modeling CMOS devices at high frequencies by utilizing a complicated substrate resistance network and extensive modification to the BSIM3v3 source code. This paper first describes a unified device model realized with a lumped resistance network suitable for simulations of both RF and baseband analog circuits; then verifies the accuracy of the model to measured data on both device and circuit levels.

Modeling of pocket implanted MOSFETs for anomalous analog behavior

Abstract: Pocket implant is widely used in deep-sub-micron CMOS technologies to combat short channel effects It, however, brings anomalously large drain-induced threshold voltage shift and low output resistance to long channel devices This creates a serious problem for high-performance analog circuits In this paper, the first physical model of these effects is proposed and verified against data from a 018 /spl mu/m technology This model is suitable for SPICE modeling

An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness

Abstract: As the gate oxide thickness is vigorously scaled down, quantization-induced charge layer thickness in MOSFETs has to be considered for accurate MOSFET intrinsic capacitance modeling for circuit simulation. We report in this paper an analytical MOSFET intrinsic capacitance model incorporating the concept of charge layer thickness, which was developed based on the self-consistent solution of the Schrodinger and Poisson equations with Fermi-Dirac statistics. The results demonstrate that this model has excellent accuracy and simulation performance.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

Abstract: The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation

Abstract: This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits

Abstract: In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.

MOS transistor modeling for RF IC design

Abstract: This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-/spl mu/m CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement.