Xiaojie Xu

Bio: Xiaojie Xu is an academic researcher from University of Electronic Science and Technology of China. The author has contributed to research in topics: MOSFET & Ohmic contact. The author has an hindex of 2, co-authored 9 publications receiving 13 citations.

A Novel SiC MOSFET Embedding Low Barrier Diode With Enhanced Third Quadrant and Switching Performance

Abstract: A novel planar gate SiC MOSFET embedding low barrier diode (LBD-MOSFET) with improved third quadrant and switching performance is proposed and characterized in this letter. The LBD-MOSFET not only exhibits about 3 times lower diode turn on voltage than the body diode, but also successfully eliminates bipolar degradation phenomena. A low potential barrier for electrons transporting from JFET region to N+ source region is formed in LBD-MOSFET owing to the existence of the depletion charge in LBD base region. Meanwhile, the gate-to-drain charge ( ${Q}_{\text {gd}}){}$ and gate-to-drain capacitance ( ${C}_{\text {gd}}){}$ of LBD-MOSFET are significantly reduced by about $21\times $ and $15\times $ in comparison with the conventional MOSFET (C-MOSFET), due to the reduction of the overlapping area of the gate and drift region. Therefore, the obtained high frequency figures of merit (HF-FOM $1= {R}_{\text {on,sp}}\times {Q}_{\text {gd}}$ and HF-FOM $2= {R}_{\text {on,sp}}\times {C}_{\text {gd}}$ ) for the LBD-MOSFET are improved by about 13 times and 9 times compared with C-MOSFET. Furthermore, a compact potential barrier analytical model based on Poisson’s Law is developed to understand the origin of low potential barrier diode in SiC LBD-MOSFET. The overall enhanced performances suggest SiC LBD-MOSFET is an excellent choice for high frequency power electronic applications.

Short-Circuit Capability Prediction and Failure Mode of Asymmetric and Double Trench SiC MOSFETs

Abstract: In this article, short-circuit capability prediction and failure mode of 1200-V-class SiC MOSFET s with a double and asymmetric trench structure are proposed under single-pulse short-circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various dc bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in a short-circuit test. For asymmetric trench SiC MOSFET s, failure modes are gate damage at lower dc bus voltages and thermal runaway at higher dc bus voltages; whereas failure mode for double trench SiC MOSFET s is thermal runaway at all dc bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the dc bus voltage and peak short-circuit current of the device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFET s by the postdecapsulation.

Silicon carbide diode with low turn-on voltage and low on resistance and manufacturing method

Abstract: The invention provides a silicon carbide diode with low turn-on voltage and low on resistance and a manufacturing method thereof. The silicon carbide diode comprises a cathode metal electrode, an N +substrate above the cathode metal electrode and an N-drift region above the N + substrate, a P-type shielding buried layer arranged above the N-drift region; a P + ohmic contact region arranged in theP-type shielding buried layer, an anode metal electrode arranged above the P + ohmic contact region, a trench gate dielectric layer arranged above the P-type shielding buried layer, a polysilicon trench gate arranged in the trench gate dielectric layer, an N+ source regions arranged between the trench gate dielectric layers, a plane gate dielectric layer arranged above the N + source regions, anda polysilicon plane gate arranged in the plane gate dielectric layer. The anode metal electrode covers the trench gate dielectric layer, the polysilicon trench gate, the N+ source region, the plane gate dielectric layer and the polysilicon plane gate. According to the invention, the three-channel accumulation type channel MOSFET and the JFET are connected in series to form the super-barrier diode, and the silicon carbide diode has the characteristics of low turn-on voltage, small on-resistance, high reverse withstand voltage, small leakage current and the like.

Design and Characteristics of an Etching Field Limiting Ring for 10kV SiC Power Device

Abstract: For ultra-high voltage SiC devices of 10kV and above, the length of conventional FLR even reaches up to millimeters, which impedes the miniaturization and development in ultra-high voltage applications. In this paper, a novel termination structure of the Etching Uniform Field Limiting Ring (EU-FLR) for 10kV SiC power device is proposed and analyzed based on the theory of charge field modulation. The blocking capability achieves at 14.2kV and the EU-FLR exhibits a reduction of more than 30% in size compared with the conventional FLRs. The voltage efficiency factor η 1 of EU-FLR is 90% and the area efficiency factor η 2 is 17.8V/μm, respectively. The influence of the pivotal structural parameters of EU-FLRs on termination protection efficiency has been analyzed and researched by TCAD Silvaco.

An Improved Composite JTE Termination Technique for Ultrahigh Voltage 4H-SiC Power Devices

Abstract: This paper presents a novel and efficient multiple-step-modulated JTE (MSM-JTE) termination technique for ultrahigh voltage (>10 kV) silicon carbide (SiC) devices, to extend the ultrahigh voltage JTE dose window and increase the breakdown voltage. MSM-JTE takes advantage of ring assisted JTE, etched JTE and space modulated JTE, to relief local electric field concentration and form a gradual decrease of effective charges overall. This is similar to lateral variation doping (VLD) technique which is widely used in silicon. A practical fabrication processes is also described. Compared with conventional TZ-JTE, MSM-JTE requires only one extra etching process and is insensitive to doping dose and energy of ion implantation. The MSM-JTE is applied to 15 kV PiN rectifier and simulated by Silvaco TCAD. The simulation result shows MSM-JTE could reach a nearly ideal maximum efficiency of 99 % and keep an efficiency of 95 % in a doping interval of 7×1012 cm−2. Tolerance to etching depth uncertainties is also high enough for process reliability and repeatability.

Degradation of Hexagonal Silicon Carbide-based Bipolar Devices

Abstract: Silicon carbide displays multiple characteristics that make it ideally suited for efficient high voltage switching devices. However, the commercialization of this technology has been hampered by degradation of SiC p-n junctions due to the expansion of Shockleytype stacking faults. The faults gradually cover most of the junction area and impede current flow. This talk will on physics and materials science of this phenomenon including: properties of faults in hexagonal SiC polytypes and their bounding dislocations, mechanism and driving force for fault expansion, and their nucleation sites. The approaches to materials growth and processing leading to elimination of this effect will be discussed.

Online Gate-Oxide Degradation Monitoring of Planar SiC MOSFETs Based on Gate Charge Time

Abstract: Gate-oxide degradation has been one of the critical reliability concerns of silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors (mosfets), which could be monitored through aging-sensitive parameters. In this article, an online gate-oxide degradation monitoring method for planar SiC mosfets is proposed by extracting gate charge time at a specific range of gate voltage. It is based on the findings that the input capacitances of planar SiC mosfets change significantly over gate-oxide degradation, which is theoretically analyzed and experimentally verified. The capacitance variations are converted into the gate charge time as the new aging-sensitive parameter. The new parameter measurement circuit is proposed and integrated into the gate driver module. The article results indicate that the new parameter varies noticeably with gate-oxide degradation and the difference of this parameter caused by junction temperature is much smaller than that caused by degradation. Besides, the parameter is immune to package degradation and load current. The condition monitoring method can be implemented online since the parameter is extracted during the off-state of SiC mosfet devices, which does not affect normal operation. The confirmatory experiment is carried out to verify the correctness of the proposed method.

A Novel SiC Asymmetric Cell Trench MOSFET With Split Gate and Integrated JBS Diode

Abstract: A novel high performance SiC asymmetric cell trench MOSFET with split gate (SG) and integrated junction barrier schottky (JBS) diode (SGS-ATMOS) is proposed for the first time. The shielding effect provided by the SG structure not only reduces the gate-drain capacitance ( ${C}_{\mathrm{gd}}$ ) but also alleviates the electric field crowding in the dielectric layer at trench corner. The integrated trench JBS diode bypasses the PiN body diode while obtaining good double protection from the SG and p-type shielding region. Therefore, not only the MOSFET but also diode performance is significantly improved for the proposed structure. Numerical analysis results show that compared with the conventional asymmetric cell trench MOSFET (Con-ATMOS), the high frequency figure of merit (HFFOM1, ${R}_{\mathrm{on}} {\cdot } {C}_{\mathrm{gd}}$ ) is reduced by 92.5% and the Baliga figure of merit (BFOM, ${BV}^{2}/R_{\mathrm{on,sp}}$ ) is increased by 57.2%, respectively. In addition, the forward conduction voltage drop ( ${V}_{\mathrm{F}}$ ), reverse recovery charge ( ${Q}_{\mathrm{rr}}$ ) and peak reverse recovery current ( ${I}_{\mathrm{rrm}}$ ) of the diode are reduced from 3.10V, $1.95\mu \text{C}$ /cm2 and 68.0A for the Con-ATMOS to 1.56V, $0.97\mu \text{C}$ /cm2 and 35.9A for the proposed SGS-ATMOS, respectively. Compared with the Con-ATMOS, the turn-on loss ( ${E}_{\mathrm{on}}$ ) and turn-off loss ( ${E}_{\mathrm{off}}$ ) of the proposed device are reduced by 33.3% and 33.0%, respectively. The ${E}_{\mathrm{on}}$ and ${E}_{\mathrm{off}}$ of the proposed device are also 33.6% and 30.0% off compared with the Con-ATMOS with external JBS diode, respectively. The temperature characteristics of the SGS-ATMOS are also discussed and it is found that the proposed device exhibits good performance at high temperature.

Effect of Threshold Voltage Hysteresis on Switching Characteristics of Silicon Carbide MOSFETs

Abstract: Threshold voltage ( ${V}_{\text {TH}}$ ) hysteresis affects the reliability of silicon carbide (SiC) MOSFETs. To evaluate the ${V}_{\text {TH}}$ hysteresis effect on switching characteristics, this article first investigates the ${V}_{\text {TH}}$ hysteresis in the static characteristics of three SiC MOSFETs with different gate structures. The results illustrate the density of the interface states in different gate structures. Then, the effect of ${V}_{\text {TH}}$ hysteresis on dynamic characteristics under varying OFF-state starting voltages ( ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ ) is evaluated by experiment. Furthermore, the effect mechanism of ${V}_{\text {TH}}$ hysteresis and ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ on switching characteristics is analyzed. Under the effect of the ${V}_{\text {TH}}$ hysteresis, a smaller ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ reduces ${V}_{\text {TH}}$ when the device turns on. This phenomenon leads to a reduction in the turn-on delay and consequently lowers the turn-on loss. Therefore, the ${V}_{\text {TH}}$ hysteresis is a significant factor for gate driver design of SiC MOSFETs.

Investigation of Failure Mechanisms of 1200 V Rated Trench SiC MOSFETs Under Repetitive Avalanche Stress

Abstract: In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and on-state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of on-state resistance caused by thermal fatigue is observed.