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Xiaojin Wei

Bio: Xiaojin Wei is an academic researcher from IBM. The author has contributed to research in topics: Heat transfer & Thermal grease. The author has an hindex of 9, co-authored 23 publications receiving 293 citations.

Papers
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Patent
22 Jul 2008
TL;DR: In this paper, an apparatus to reduce a thermal penalty of a 3D die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environments, which is coupled to the substrate in a stacking direction.
Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.

52 citations

Patent
13 May 2008
TL;DR: In this paper, a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate, and the liquid cooler is mechanically coupled to the package substrate through a metallic stiffener structure.
Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

50 citations

Patent
08 Jul 2010
TL;DR: In this paper, a die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack.
Abstract: A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.

44 citations

Patent
04 Mar 2015
TL;DR: In this paper, a thermally conductive cover over a plurality of electronic components and an enclosure in which the electronic components reside is provided with enhanced heat dissipation capabilities, which facilitates spreading and dissipating of the transferred heat outwards.
Abstract: Electronic packages are provided with enhanced heat dissipation capabilities The electronic package includes a plurality of electronic components, and an enclosure in which the electronic components reside The enclosure includes a thermally conductive cover overlying the electronic components At least one heat transfer element is coupled to, or integrated with, the thermally conductive cover and resides between a main surface of the cover and at least one respective electronic component of the plurality of electronic components A thermal interface material is disposed between the heat transfer element(s) and the respective electronic component(s), and facilitates conductive transfer of heat from the electronic component(s) to the thermally conductive cover through the heat transfer element(s) The thermally conductive cover facilitates spreading and dissipating of the transferred heat outwards, for instance, through a surrounding tamper-respondent sensor and/or a surrounding encapsulant

34 citations

Proceedings ArticleDOI
Xiaojin Wei1, Kamal K. Sikka1
05 Jul 2006
TL;DR: In this paper, a thermal model has been developed consisting of a heated chip integrated with a substrate, thermal interface material, vapor chamber lid and heat sink, where the model can predict the temperature profile fairly well as compared with the results of a detailed numerical model.
Abstract: As the heat density on the chip increases and heat dissipation is more localized, there are growing interests in developing alternative heat spreading devices. Vapor chambers have been used as heat spreading devices in heat sink bases. Before considering for integration into package heat spreaders or lids, the compatibility of the vapor chamber with the assembly processes would have to be assessed. However, before embarking down that path, this paper attempts to quantify the thermal benefit, if any, of vapor chamber heat spreaders compared to commonly used solid metal heat spreaders. A thermal model has been developed consisting of a heated chip integrated with a substrate, thermal interface material, vapor chamber lid and heat sink. The vapor chamber is represented by multiple block layers with effective thermal conductivities. It is revealed that the model can predict the temperature profile fairly well as compared with the results of a detailed numerical model. A sensitivity study shows that the thermal performance is sensitive to the effective thermal conductivity of the wick structure and insensitive to the effective thermal conductivity of the vapor space. A parametric study indicates that the vapor chamber heat spreader out-performs a copper block of the same dimension when the footprint size is larger than a certain value. It is concluded that vapor chamber is most effective in spreading heat over large areas. Consequently, it is suitable for applications where more surface area is desired due to reasons such as low heat transfer coefficients

32 citations


Cited by
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Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Journal ArticleDOI
TL;DR: In this paper, an optimized heat pipe thermal management system (HPTMS) is proposed for fast charging lithium ion battery cell/pack, and a numerical model is developed and comprehensively validated with experimental results.

249 citations

Patent
29 Nov 2012
TL;DR: In this article, a power semiconductor device such as a diode and a thyristor with at least one pn junction between a pair of main surfaces is considered, where a first main electrode is formed on the surface of one of the main surfaces and a second main electrode has been formed on surface of the other surface.
Abstract: The present invention relates to a power semiconductor device such as a diode and thyristor. In a semiconductor device such as a diode and thyristor having at least one pn junction between a pair of main surfaces, a first main electrode is formed on the surface of one of the main surfaces and a second main electrode is formed on the surface of the other one of the main surfaces. A semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode to the second main electrode. Since the distribution of carrier density in the conduction state can be flattened according to the invention, the reverse recovery charge can be reduced substantially without causing the ON-state voltage to increase.

158 citations

Patent
23 Jul 2010
TL;DR: In this paper, a microelectronic unit includes an integrated circuit chip, having a semiconductor region of monocrystalline form, with an active circuit element adjacent the front surface, a rear surface remote from the front surfaces, and a conductive via which extends towards the rear surface.
Abstract: A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via. A rear contact can be electrically connected to the conductive via and exposed at the rear surface for electrical connection with an external circuit element, such as another like microelectronic unit, a microelectronic package, or a circuit panel.

120 citations

Patent
Yi-Li Hsiao1, Chen-Hua Yu1, Da-Yuan Shih1, Chih-Hang Tung1, Chun Hui Yu1 
09 Sep 2010
TL;DR: An apparatus for cooling a stacked die package comprises a first die provided above a substrate, a second die above the first die, a cooling fluid in fluid communication with the first and the second die, the cooling fluid for absorbing thermal energy from the first, second and third dies.
Abstract: An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wherein the outputs of the first and second temperature sensors relative to each other are indicative of a level of the cooling fluid.

96 citations