Xie Shigen

Bio: Xie Shigen is an academic researcher. The author has contributed to research in topics: Field-programmable gate array & Phased array ultrasonics. The author has an hindex of 1, co-authored 2 publications receiving 14 citations.

Design and FPGA implementation of flexible and efficiency digital down converter

Abstract: Digital down converter (DDC) is the one of the key technologies in the field of software define radio (SDA). Compared with traditional ASIC DDC devices, DDCs implemented by FPGA have more flexible frequency and phase characteristics and higher precision computation. The paper designed and implemented DDC with above advantages on Xilinx FPGA Virtex-5. Through analyzing the key points of DDC theory and MATLAB simulation analysis, DDC with across clock region and FIFO interface characteristics is designed using Xilinx ISE. Some important and practical implementation details are given in this paper. And finally presents one application of DDC in communication systems by the portions given in this document.

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

Abstract: Software Defined Radio (SDR) has the flexibility to modify the characteristics of the receiving and transmitting radio device, without physically adjusting the hardware, due to development in the system Because of the increasing need for wireless communication applications so as to enable consumers to communicate anywhere through information led to the emergence of many communication devices to include the large amount of applications that every one of the devices needs power and thereby increase the total power This study confirms that the wireless communication system for secured transmit data, fast and inexpensive; can be done by implementing using Partial Reconfiguration (PR) modern technology in FPGA developing based on SDR The Speed and performance can be improved The area also can be decreased The new Xilinx, Vertex Series FPGA, provides the provision of PR The power consumption can be reduced by applying power reduction techniques in the blocks The combination of MATLAB (Simulink and M-file) and Simulink HDL Coder offers flexible capabilities for analysis, design; simulation, implementation, and verification With all these capabilities, in a single system to reduce the time spent tuning for reducing the algorithms and models during rapid prototyping and experimentation and less time on HDL coding

Design and Implementation of a Reconfigurable Digital Down Converter for 4G Systems Using MATLAB and FPGA- A Review

Abstract: With the rapid growth in the technology, the generations that are evolved involve 1G, 2G,3G, 4G and 5G technologies. The Digital Down Converter (DDC) is one of the important parts of a 4G receiver system. Development of an efficient DDC architecture is highly important becausethe applications are increasingly demanding for high efficiency and less power consumption. Inthis paper, a reconfigurable ddc architecture is introduced which reduces the hardware resources used. It consists of a mixer, decimator and a FIR filter. The proposed architecture is compared with the existing architecture. Simulations can be performed using MATLAB and implementation is proposed on FPGA using Verilog or VHDL code. Verilog is widely used since it is user friendly and easily understandable. The proposed DDC reduces the gate density.

Design of digital down converter using Computation sharing multiplier architecture

Abstract: In the field of software defined radio, DDC plays a pivotal role in defining the optimum sampling rate without encountering any loss of information The essential part of any DDC is the low pass filtering operation Traditionally CIC filters are used for the design of low pass filters in the DDC which poses disadvantages in the area occupied and delay in the FPGA devices This paper focuses on the shared resource technique for the design of the FIR filter operation The technique involved in designing the filter is the usage of a special type of multiplier called Computation sharing multiplier(CSHM) This technique enhances the performance of the DDC and also reduces the component utilization in FPGA Xilinx ISE is used to simulate and synthesize the design

Research and implementation of a high performance parallel computing digital down converter on graphics processing unit

Abstract: Summary Digital down converter (DDC) is a time-intensive and data-intensive computing task and considered as the key technology in software defined radio. This paper proposes a high-performance implementation of DDC on a graphics processing unit (GPU) using CUDA, which is composed of a numerically controlled oscillator stage, a cascaded integrator-comb (CIC) decimation filter stage, and a finite impulse response (FIR) filter stage. The GPU implementation and optimizing of all the stages are studied in detail. Additionally, for handling a long-duration signal, the signal data sequence is truncated into segments; the overlap-save and overlap-add mechanisms were applied in CIC stage and FIR stage, respectively. Finally, experiments were conducted to evaluate the performance of GPU-based DDC with respect to a sequential version CPU implementation and an OpenMP implementation (16 threads). Experimental results demonstrate that the DDC achieves significant improvements on the GPU; the maximum speed ups in numerically controlled oscillator stage, CIC stage, and FIR stage can achieve more than 1242, 527, and 179 times, including data-transfer, kernel execution, and other processing operations; the overall speed up of DDC can achieve more than 180. In the meantime, the speed ups of GPU implementation are far above the OpenMP implementation (about 2.5-6.4 times).

Low power Transceiver Structure for Wireless and Mobile Systems Based SDR Technology Using MATLAB and System Generator

Abstract: This paper presents the design and implementation of Software Defined Radio (SDR) transceiver based 16-QAM as one of the key techniques in structure of wireless and mobile communication system. The widely used of QAM in adaptive modulation due to efficient power and bandwidth force the researchers to found better and easy design by use the available software like MATLAB in order to advance the idea of software defined radio. The setting of parameter for random generator, QAM modulation and demodulation, AWGN wireless channel are provided. The Error rates of QAM system against the signal-to-noise ratio are used to evaluate the QAM system. The implementation results shows the system capability to transmitand receive intermediate frequency of 40 MHZ keeping the power under limited FPGA Slices and look up table (LUT).