This work presents a real-time 100Base-TX Ethernet physical layer (PHY) transceiver chip implemented in a 180-nm technology. The PHY chip implements highly accurate hardware timestamping by using an 8-bit digital-to-phase converter (DPC) generating 256 phases of the 125 MHz system clock. Using these clock phases, spaced 31.25 ps apart from each other, phase relationships can be evaluated to timestamp ingress and egress frames with improved resolution. Connected by up to 120-m-long category five unshielded twisted-pair cables, two of these PHY chips are used to demonstrate the synchronization in a two-node scenario. A proportional–integral (PI)-clock servo is used at the slave for the synchronization. To optimize the performance, the parameters of the controller need to be chosen carefully. To do so, a simple model is used to find a suitable bandwidth of the controller as a tradeoff between the noise of the timestamping and the noise of the oscillator. All in all, a synchronization accuracy with a standard deviation of only 64 ps and a mean offset of well below 100 ps is achieved in the given scenario. To the best of our knowledge, this is the highest synchronization accuracy over copper-based Ethernet reported to date.

Subnanosecond Time Synchronization Using a 100Base-TX Ethernet Transceiver and an Optimized PI-Clock Servo

This article presents a systematic empirical modeling approach in fully depleted silicon-on-insulator (FDSOI) CMOS for large-signal simulation in power amplifier applications. The model is constructed from multibias S-parameter measurements up to 67 GHz. The frequency dispersions in transconductance and output conductance are addressed by two independent radio frequency (RF) current sources. Angelov’s current formula is modified to adapt to the FDSOI transistors. Load-pull measurements are performed for the large-signal verification in a non-50- $\Omega $ environment. The model accurately predicts the nonlinear characteristics of the device under test and the harmonic components. The time-domain waveforms also show excellent agreement to the simulation.

Empirical Large-Signal Modeling of mm-Wave FDSOI CMOS Based on Angelov Model

This article presents two millimeter-wave frequency reconfigurable dual-band CMOS power amplifiers (PAs) for fifth-generation (5G) communications comprising a single-stage dual-band PA and a two-stage dual-band PA for higher gain. The PAs cover multiple 5G communication bands, n257 (26.5–29.5 GHz) and n260 (37–40 GHz), which use reconfigurable transmission line transformers (TLTs) for output, input, and interstage matching networks. These matching networks allow the operating frequency bands to be changed, thereby achieving optimum performance. The integrated mode selection switches in the transformers reconfigure the inductances of the TLTs to cover two frequency bands, which allows the PAs to have small overall chip sizes. These are fabricated in a 28-nm bulk CMOS process. The single-stage dual-band PA achieves 20.2-/19.1-dBm saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {sat}}$ </tex-math></inline-formula> ), 18.7-/18.6-dBm 1-dB compressed output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {1 dB}}$ </tex-math></inline-formula> ), and 33.6%/32% peak power-added efficiency (PAE) at 26.5 and 37 GHz, respectively, while occupying a chip area of 0.11 mm 2 . The two-stage dual-band PA achieves 19.1-/19.5-dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {sat}}$ </tex-math></inline-formula> , 17-/17.8-dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {1 dB}}$ </tex-math></inline-formula> , and 31.3%/30.5% PAE at 26.5 and 37 GHz, respectively, while occupying a chip area of 0.165 mm 2 . Both PAs are tested under 64-quadrature amplitude modulation signals with a 100-MHz channel bandwidth. The single-stage PA achieves 14.7- and 12.3-dBm average output powers ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {avg}}$ </tex-math></inline-formula> ) with −25.1- and −25-dB error vector magnitudes (EVMs) at 26.5 and 37 GHz, respectively. The two-stage PA achieves 12.3- and 11.6-dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {avg}}$ </tex-math></inline-formula> ’s with −25.3- and −25.1-dB EVMs at 26.5 and 37 GHz, respectively.

Millimeter-Wave Frequency Reconfigurable Dual-Band CMOS Power Amplifier for 5G Communication Radios

A broadband SiGe power amplifier (PA) with double gain peaks for 5G applications is presented. The differential structure is widely adopted in millimeter-wave circuit design to decrease the impact of the source parasitic inductance that is induced by the bonding wires. Since differential PA results in a higher impedance transformation ratio of the matching network, differential PAs generally have narrower bandwidth than single-ended PAs. Through the bandwidth analysis of the matching network, the transformer used for interstage matching is elaborately designed to ease gain fluctuations. By controlling the stationary points of impedance transformation, the maximum available gain characteristic of a transistor, which decreases with increasing frequency, can be compensated. The gain curve of PA, thus, has double gain peaks within operational frequencies to make its frequency responses as flat as possible. The proposed PA for the frequency band from 27 to 37 GHz is fabricated in a standard 130-nm SiGe BiCMOS process, which occupies 0.36 mm2. Under the 2.5-V voltage supply, the SiGe PA exhibited a power gain of 33.5 dB and output power of 21.3 dBm with 24% power-added efficiency at 31 GHz. It achieves a 34% 3-dB small-signal $S_{21}$ bandwidth from 27.3 to 38.5 GHz.

A SiGe Power Amplifier With Double Gain Peaks Based on the Control of Stationary Points of Impedance Transformation

This work presents a broadband low-voltage binary-phase-shift-keying (BPSK) modulator operating in the D-band. The modulator is intended for a phase-modulated continuous-wave (PMCW) radar transmitter with a chip rate of up to 12.5 Gb/s and integrated into an advanced 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. The circuit covers a bandwidth of 34 GHz at a carrier frequency of 140 GHz with a maximum conversion gain of 2.5 dB. A 1 dB output compression point of -7.2 dBm is reached while consuming 27 mW DC-Power at a supply voltage of only 0.8 V and a circuit core area of 0.051 mm2.

A Low-Voltage Broadband D-Band BPSK Modulator for a PMCW Radar Transmitter in 22 nm FDSOI

This paper presents a high-gain dual-band low noise amplifier (LNA) for 5G wireless systems. The LNA is implemented in 22nm FD-SOI CMOS technology and operates simultaneously in the 28 GHz and 38 GHz millimeter-wave 5G bands. The circuit consists of three cascaded cascode amplifier stages. To obtain a dual-band response, gain peaking technique was implemented. Single-band matching networks were used to match the circuit input and inter-stage at different target frequencies. A dual-band matching network at the output ensures low return losses at both frequencies of interest. For a power consumption of 13. 6mW from a 1. 6V supply, the LNA provides a peak gain of 25. 1dB and a minimum noise Figure of 3.6 dB. The measured gain at 28 GHz and 38 GHz is greater than 22 dB. For a competitive power consumption, the LNA compares well against previously reported designs by showing one of the highest measured gain, gain-bandwidth product (GBW) and comparable noise figure.

A 28 GHz and 38 GHz Dual-Band LNA Using Gain Peaking Technique for 5G Wireless Systems in 22 nm FD-SOI CMOS

This paper presents a high-gain, dual-band power amplifier for 5G wireless systems, which supports a simultaneous operation at 28 GHz and 38 GHz. The circuit is based on two transistor-stack-amplifier stages, and is implemented in a 22 nm FD-SOI technology. Dual-band matching networks based on transmission lines and capacitors were used to realize the dual-band characteristic. For a power consumption of 318 mW from 2.7 V voltage supply, the power amplifier provides a gain of 31.7 dB, saturated output power of 19.4 dBm, output power 1 dB compression point of 15.7 dBm, maximum power-added-efficiency of 26.4% at 28 GHz, while a gain of 29.2 dB, saturated output power of 19.2 dBm, output power 1 dB compression point of 15.2 dBm, maximum power-added-efficiency of 25.1% were measured at 38 GHz. The power amplifier shows a measured gain-bandwidth product of 272.3 GHz. The power amplifier compares well against previously reported designs by showing one of the highest measured gain and gain-bandwidth product while still having a competitive performance in the other figures of merit. To the best of authors’ knowledge, this is the first power amplifier using dual-band matching technique to provide a dual-band operation at 5G millimeter-wave bands.

A 28 GHz and 38 GHz High-Gain Dual-Band Power Amplifier for 5G Wireless Systems in 22 nm FD-SOI CMOS

This work presents an integrated mm-wave transmitter front-end with independent in-phase and quadrature paths for carrier frequencies around 180 GHz. The up-conversion units consist of a double-balanced active mixer with baseband (IF) buffer, local oscillator (LO) driver and RF power amplifier (PA). A passive 90° hybrid generates the quadrature LO signal and a power combiner joins the PA outputs. The IF-to-RF conversion gain is 10 dB, with an RF bandwidth of 80 GHz. The design supports binary and higher order modulation schemes and exhibits an IF input referred 1-dB compression point of −11 dBm. The saturated output power is 3.5 dBm per path and an LO level of −5 dBm is sufficient for an optimal operation. The total power consumption is 151 mW per path. The final chip occupies an area of 1.4 mm2 and is fabricated in a 130 nm SiGe BiCMOS process with a maximum oscillation frequency of 450 GHz. The main application of this circuit is ultra-wideband short-range communication with data rates beyond 100 Gbit/s.

Direct-Conversion I-Q Transmitter Front-End for 180 GHz with 80 GHz Bandwidth in 130 nm SiGe

This work presents an analogue equaliser with digital tuning. It compensates the losses introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline wander (BLW). The equaliser is designed for Fast Ethernet with a symbol rate of 125 MHz. A g
 m
-C filter, based on three first-order high pass filters, is used to compensate the cable loss. To minimise power consumption, three operational transconductance amplifiers (OTAs) are merged into a novel multi-input OTA structure. Additionally, a robust digital control logic is presented to automatically adjust the parameters of the equaliser for different cable lengths. A fast settling time below 250 µs is demonstrated for different scenarios. The equaliser is fabricated as part of a Fast Ethernet PHY chip in a 180 nm CMOS technology of GLOBALFOUNDRIES. Measurement results demonstrate error-free data transmission (bit error rate below 10
 −12
) for cable lengths up to 120 m. The power consumption of the analogue equaliser ranges from 2.3 mW (short cable) to 6.5 mW (120 m cable). To the best of the authors’ knowledge, this is the lowest power consumption of an analogue equaliser for Fast Ethernet, supporting additional BLW and flat loss compensation reported to date.

Low power analogue equaliser with adaptive digital tuning for fast ethernet

This paper presents a high-gain broadband power amplifier for 5G wireless systems, which provides a gain above 10 dB from 21 GHz to 39.5 GHz, and is implemented in a 22 nm FD-SOI technology. The circuit is based on two stacked amplifier stages which are connected with lumped-element matching networks. For a power consumption of 228 mW from a 2.4 V voltage supply, the amplifier provides 25 dB of peak gain, maximum saturated output power of 16.8 dBm, output power in 1 dB gain-compression of 13 dBm, and maximum power-added-efficiency of 19.8%. The power amplifier compares well against previously reported designs by showing the highest measured gain and gain-bandwidth product while still having comparable performance in the other figures of merit.

Xin Xu

Papers

A 28 GHz and 38 GHz Dual-Band LNA Using Gain Peaking Technique for 5G Wireless Systems in 22 nm FD-SOI CMOS

A 28 GHz and 38 GHz High-Gain Dual-Band Power Amplifier for 5G Wireless Systems in 22 nm FD-SOI CMOS

Direct-Conversion I-Q Transmitter Front-End for 180 GHz with 80 GHz Bandwidth in 130 nm SiGe

Low power analogue equaliser with adaptive digital tuning for fast ethernet

A 21-39.5 GHz Power Amplifier for 5G Wireless Systems in 22 nm FD-SOI CMOS