Xing Zhou

Bio: Xing Zhou is an academic researcher from Nanyang Technological University. The author has contributed to research in topics: MOSFET & Threshold voltage. The author has an hindex of 20, co-authored 140 publications receiving 1362 citations.

A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology

Abstract: A novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated. It is shown that by adding a layer of material with a larger workfunction to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability. The threshold voltage roll-off can be compensated and tuned by controlling the length of this second gate. The new structure has great potential in breaking the barrier of deep-suhmicron MOSFET's scaling beyond 0.1 /spl mu/m technologies.

Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering

Abstract: The novel characteristics of a new type of MOSFET, the hetero-material gate field-effect transistor (HMGFET), are explored theoretically and compared with those of the compatible MOSFET. Two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology. The two-dimensional (2-D) numerical simulations reveal that the HMGFET demonstrates extended threshold voltage roll-off to much smaller length and shows simultaneous transconductance enhancement and suppression of short-channel effects (SCEs) [drain-induced barrier-lowering (DIBL) and channel-length modulation (CLM)] and, more importantly, these unique features could be controlled by engineering the material and length of the gate. This work demonstrates a new way of engineering ultrasmall transistors and provides the incentive and guide for experimental exploration.

A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling

Abstract: A new definition of MOSFET threshold voltage is proposed, namely, the "critical-current at linear-threshold" method, which has a unique solution and is very simple to measure. This definition gives consistent values of threshold voltage for different regions of operation at long channel, and contains the information on short-channel effects at short channel, which is very useful for deep-submicron MOS device characterization and modeling. The proposed method effectively removes ambiguity of de facto industry standard of the constant-current method for MOS threshold voltage.

Excimer laser-annealed dopant segregated Schottky (ELA-DSS) Si nanowire gate-all-around (GAA) pFET with near zero effective Schottky barrier height (SBH)

Abstract: We demonstrate excimer laser annealed dopant segregated Schottky (ELA-DSS) junction on gate-all-around (GAA) silicon nanowire pFETs. The metal-semiconductor junction interfacial doping is increased by two-fold with the ELA method. On silicon nanowire, the method achieves an effective Schottky barrier height (SBH) of nearly zero, improves the short channel performance and reduces the parasitic resistance of the fabricated devices, leading to an average improvement of 37% in I ON as compared to the devices fabricated without laser annealing.

Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs in the Subthreshold Region

Abstract: The low-frequency noise (LFN) in the subthreshold region of both n- and p-type gate-all-around silicon nanowire transistors (SNWTs) is investigated. The measured drain-current noise spectral density shows that the LFN in this regime can be well described by the mobility-fluctuation model due to the volume-inversion conduction behavior, and the Hooge parameter is extracted. The LFN in the SNWTs with channels oriented in lang010rang and lang110rang directions is compared. It shows that the observed mobility enhancement in the lang010rang direction for p-type transistors leads to a corresponding increase of the LFN level in the lang010rang direction compared with that in the lang110rang direction.

System comprising a semiconductor device and structure

Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Semiconductor device and structure

Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.