Xiong Zhou

Bio: Xiong Zhou is an academic researcher from University of Electronic Science and Technology of China. The author has contributed to research in topics: Successive approximation ADC & Effective number of bits. The author has an hindex of 6, co-authored 28 publications receiving 112 citations.

Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators

Abstract: Subthreshold amplifiers suffer from the limited voltage headroom which leaves little space for conventional analog techniques to enhance performance and efficiency. This paper presents an evolution process of implementing conventional structures with inverters, allowing ultralow-voltage operation with increased flexibility in adopting traditional circuit techniques. Based on the proposed inverter-based elementary structure and CMFB, both the Miller-compensated (MC) operational transconductance amplifier (OTA) and the feedforward-compensated (FFC) OTA achieve significantly improved performance as compared to previous works. The proposed amplifier techniques are verified in $\Delta \Sigma $ modulator (DSM) design, with MC-OTA for a DT-DSM and FFC-OTA for a CT-DSM, both fabricated in a 0.13- $\mu \text{m}$ CMOS. The 0.3-V DT-DSM achieves 74.1-dB SNDR, 83.4-dB SFDR and 20-kHz bandwidth with 79.3- $\mu \text{W}$ power, resulting in a Schreier figure of merit (FoM) of 158 dB. The 0.3-V CT-DSM achieves 68.5-dB SNDR, 82.6-dB SFDR, and 50-kHz bandwidth with 26.3- $\mu \text{W}$ power, leading to a Schreier FoM of 161 dB. Both DSMs exhibit highly competitive performance among sub-0.5-V designs, validating the proposed subthreshold amplifier techniques.

A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator is presented in this paper. The relationship between the input voltage and the number of oscillation cycles (NOC) to reach a VCO-comparator decision is explored, implying an inherent coarse quantization in parallel with the normal comparison. The NOC as a design parameter is introduced and analyzed with noise, metastability, and tradeoff considerations. The NOC is exploited to bypass a certain number of SAR cycles for higher power efficiency of VCO-based SAR ADCs. To cope with the process, voltage, and temperature (PVT) variations, an adaptive bypassing technique is proposed, tracking and correcting window sizes in the background. Fabricated in a 40-nm CMOS process, the ADC achieves a peak effective number of bits of 9.71 b at 10 MS/s. Walden figure of merit (FoM) of 2.4–6.85 fJ/conv.-step is obtained over a wide range of supply voltages and sampling rates. Measurement has been carried out under typical, fast-fast, and slow-slow process corners and 0 °C–100 °C temperature range, showing that the proposed ADC is robust over PVT variations without any off-chip calibration or tuning.

A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS

Abstract: An 8-bit SAR ADC capable of working under 160mV supply voltage is presented. To facilitate the ultra-low voltage comparator, a novel inverter-based amplifier is proposed and a dynamic latch with both gate and bulk driven input is exploited. An improved switching technique utilizing clock boosting and device stacking is employed for the ultra-low voltage sampling network. Implemented in a 0.13μm CMOS, the fabricated ADC works from 40kS/s to 400kS/s sampling rate under 160mV to 300mV supply voltage, respectively. Drawing 670nW from a single 160mV supply, the ADC achieves 0.5LSB DNL, 0.62LSB INL, 61.1dB SFDR and 7.3bit ENOB at a near-Nyquist input frequency of 19.7 kHz. To the best of authors' knowledge, this is one of the lowest reported supply voltages in analog design.

A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration

Abstract: This article presents a 14-bit 4-MS/s voltage-controlled oscillator (VCO)-based successive approximation register (SAR) analog-to-digital converter (ADC), where the metastability of the VCO-based comparator is exploited for the background calibration of mismatch errors. A closed-form behavioral analysis of VCO-based comparators has been studied in the presence of noise, showing that the metastability is of unique characteristics as compared to voltage-domain comparators, and the metastability can be evaluated quantitatively by observing the number of oscillation cycles. Deep metastability (DM) indicates a condition where the signal and noise are sufficiently small as compared to mismatch errors, based on which an analog background calibration technique is proposed. A decision stabilizer is employed to deal with the limit-cycle oscillations (LCOs). Fabricated in a 40-nm CMOS technology, the ADC prototype exhibits peak signal-to-noise-and-distortion ratio (SNDR) of 78.7 dB and >93-dB spurious-free dynamic range (SFDR) across nine samples. At 2 and 4 MS/s, the ADC, including calibration logic, consumes only 94 and $157~\mu \text{W}$ from a 1.1-V supply, achieving a peak Schreier figure of merit (FoM) of and 177.7 dB, respectively.

A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAs

Abstract: This paper presents a high-resolution ΔΣ modulator which is capable of operation under supply voltage as low as 250mV. A novel subthreshold inverter-based OTA is proposed and exploited in the switched-capacitor (SC) integrators, permitting a satisfied noise-shaping performance in the 4th-order feed-forward topology. With each stage's coefficient optimized, the integrators' internal swings and the distortion power stemming from OTAs' gain nonlinearity are minimized. Implemented in a 0.13μm CMOS with an OSR of 64 and a sampling frequency (fs) of 1.28MHz, this design achieves a measured DR of 77.0dB, SNDR of 73.3dB, and SFDR of 85.0dB over a 10kHz bandwidth. To the best of authors' knowledge, it appears to be the converter with highest SNDR observed among sub -0.5V designs.

A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

Abstract: This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage $({\rm V}_{\rm cm})$ and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed under an ultra-low voltage of 0.3 V. In addition, by employing asymmetric logic in SAR control, the leakage power is reduced with the penalty of slight conversion speed degradation. The test chip fabricated in 90 nm CMOS occupied a core area of 0.03 ${\rm mm}^{2}$ . With a single 0.3 V supply and a Nyquist rate input, the prototype consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bit and a SFDR of 78.2 dB, respectively. The operation frequency is scalable up to 2 MS/s and power supply range from 0.3 V to 0.5 V. The resultant FOMs are 1.17-to-1.78 fJ/conv.-step.

Thermal Release Transfer Printing for Stretchable Conformal Bioelectronics.

Abstract: Soft neural electrode arrays that are mechanically matched between neural tissues and electrodes offer valuable opportunities for the development of disease diagnose and brain computer interface systems. Here, a thermal release transfer printing method for fabrication of stretchable bioelectronics, such as soft neural electrode arrays, is presented. Due to the large, switchable and irreversible change in adhesion strength of thermal release tape, a low-cost, easy-to-operate, and temperature-controlled transfer printing process can be achieved. The mechanism of this method is analyzed by experiments and fracture-mechanics models. Using the thermal release transfer printing method, a stretchable neural electrode array is fabricated by a sacrificial-layer-free process. The ability of the as-fabricated electrode array to conform different curvilinear surfaces is confirmed by experimental and theoretical studies. High-quality electrocorticography signals of anesthetized rat are collected with the as-fabricated electrode array, which proves good conformal interface between the electrodes and dura mater. The application of the as-fabricated electrode array on detecting the steady-state visual evoked potentials research is also demonstrated by in vivo experiments and the results are compared with those detected by stainless-steel screw electrodes.

A 0.3-V CMOS Biofuel-Cell-Powered Wireless Glucose/Lactate Biosensing System

Abstract: This paper presents a self-powered wireless physiochemical sensing system for monitoring of glucose or lactate in bodily fluids. The biosensor chip consists of a duty-cycled biofuel cell (BFC) maximum power point tracker analog front end, a passive $\Delta \!\Sigma $ analog-to-digital converter (ADC), an RF power oscillator transmitter using a 1-cm external loop antenna, digital data storage, and timing and clock generation circuitries, all designed to operate from the dynamic 0.3-V BFC output voltage. The biosensor chip, implemented in 65-nm CMOS and exclusively powered via an enzymatic BFC, can successfully detect changes in glucose/lactate concentration between 2.5 and 15 mM, for the first demonstration of an integrated self-powered chemical biosensing system with digital wireless readout. The biosensor consumes an average power of 1.15 $\mu \text{W}$ .

Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators

Abstract: Subthreshold amplifiers suffer from the limited voltage headroom which leaves little space for conventional analog techniques to enhance performance and efficiency. This paper presents an evolution process of implementing conventional structures with inverters, allowing ultralow-voltage operation with increased flexibility in adopting traditional circuit techniques. Based on the proposed inverter-based elementary structure and CMFB, both the Miller-compensated (MC) operational transconductance amplifier (OTA) and the feedforward-compensated (FFC) OTA achieve significantly improved performance as compared to previous works. The proposed amplifier techniques are verified in $\Delta \Sigma $ modulator (DSM) design, with MC-OTA for a DT-DSM and FFC-OTA for a CT-DSM, both fabricated in a 0.13- $\mu \text{m}$ CMOS. The 0.3-V DT-DSM achieves 74.1-dB SNDR, 83.4-dB SFDR and 20-kHz bandwidth with 79.3- $\mu \text{W}$ power, resulting in a Schreier figure of merit (FoM) of 158 dB. The 0.3-V CT-DSM achieves 68.5-dB SNDR, 82.6-dB SFDR, and 50-kHz bandwidth with 26.3- $\mu \text{W}$ power, leading to a Schreier FoM of 161 dB. Both DSMs exhibit highly competitive performance among sub-0.5-V designs, validating the proposed subthreshold amplifier techniques.

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

Abstract: This paper presents a low-voltage and power-efficient 10 bit successive-approximation register (SAR) analog-to-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a time-domain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm2. At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of $0.3~\mu \text {W}$ to $2.5~\mu \text {W}$ and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step.