Author

# Xiuqin Chu

Bio: Xiuqin Chu is an academic researcher from Xidian University. The author has contributed to research in topic(s): Decoupling capacitor & Capacitor. The author has an hindex of 4, co-authored 10 publication(s) receiving 48 citation(s).

##### Papers
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Journal ArticleDOI
, Yang Liu1
TL;DR: In this article, the authors presented a modeling approach for power/ground planes with decoupling capacitors based on the resonant cavity model, where decoupled capacitors are divided into segments according to port coefficients, capacitance, number of decouplings, and the frequency response of each mode of the model.
Abstract: Based on the resonant cavity model, this paper presents a modeling approach for power/ground planes with decoupling capacitors. A bare plane pair is first modeled by the resonant cavity model. Then, decoupling capacitors are divided into segments according to port coefficients, capacitance, the number of decoupling capacitors, and the frequency response of each mode of the resonant cavity model. To get the model of the plane pair with decoupling capacitors, divided segments are incorporated into the resonant cavity model. By this way, not only the influence of decoupling capacitors on each single mode, but also the frequency responses of capacitors in each mode can be reflected. By being incorporated with the segmentation method and the physics-based modeling method, this modeling method can be extended to handle the irregular-shaped and multilayered power/ground plane with capacitors, respectively. Based on the impedance distribution throughout the whole power/ground plane pair, the effective decoupling radius of a capacitor and its variation trends with frequency, capacitance, and parasitic parameters are extracted and analyzed.

15 citations

Journal ArticleDOI
, Yang Liu1
TL;DR: In this paper, it is shown that the conversion coefficient is a constant when the radius of the decoupling capacitor is taken as the per unit length of the meshed model.
Abstract: As the clock frequency of a chip increases, the on-chip decoupling capacitor must be placed closer to the load to be effective A method of efficiently defining the location of capacitor placement to meet specified noise limits is presented Based on a single RL line model for the power distribution system, charging radius of the decoupling capacitor is calculated under the constraint of the target noise but not the constraint of being fully charged Under the constraints of the length of the charging path and the target noise, discharging radius of the decoupling capacitor is figured out The conversion coefficient that converts the radii of a decoupling capacitor in a single RL line model into the equivalent one in a meshed model is presented based on the expression that can exactly compute the impedance between any two points on an infinite meshed network In this paper, it is shown that the conversion coefficient is a constant when the radius of the decoupling capacitor is taken as the per unit length of the meshed model

14 citations

Journal ArticleDOI
, Yang Liu1
TL;DR: Based on the resonant cavity algorithm, a method is presented to model the multilayered power/ground planes with stitching vias at the high-speed packages and the printed circuit board and it is obtained that the remainder plane pairs act as a multiport load to the plane pair where the current load is located on.
Abstract: Based on the resonant cavity algorithm, a method is presented to model the multilayered power/ground planes with stitching vias at the high-speed packages and the printed circuit board. A multilayered structure can be seen as a combination of two basic units: adjacent planes with a different reference voltage and that with the same reference voltage. Then, the behaviors of the switching current in and the physics-based models for the multilayered power/ground planes with different basic units are presented. By analyzing the influence of stitching vias to the return path of the switching current in the multilayered structure, it is obtained that the remainder plane pairs act as a multiport load to the plane pair where the current load is located on. The algorithm for a plane pair with a multiport load is presented on the basis of the resonant cavity algorithm to efficient mode the multilayered power/ground planes. At the same time, this modeling method can be used in auto-decoupling design to consider the placements of decoupling capacitors. The modeling method is corroborated by the comparison with a 3-D electromagnetic commercial tool with wideband Z-parameter computation from dc to 10 GHz.

6 citations

Patent
21 Sep 2016
TL;DR: In this article, a power distribution network design method based on a decoupling region of decoupled capacitors is proposed. But the problem of the installation position of the decouplings capacitor cannot be solved, and a rapid, simple and convenient method is provided for selection and placement of the capacitor in the power distribution networks.
Abstract: The invention discloses a power distribution network design method based on a decoupling region of a decoupling capacitor. The power distribution network design method comprises the steps of: firstly, based on a resonant cavity model, modeling a power ground plane with decoupling capacitors; based on the modeling method, calculating out transverse and longitudinal decoupling radii of the decoupling capacitors; according to a frequency point corresponding to the maximum amplitude of an impedance of an input output port, selecting the required decoupling capacitor, and according to the transverse and longitudinal decoupling radii of the decoupling capacitor, selecting an installation position of the decoupling capacitor; and finally, drawing an impedance curve of a power distribution network. According to the invention, the problem that in the power distribution network design, the installation position of the decoupling capacitor cannot be obtained is solved; a rapid, simple and convenient method is provided for selection and placement of the decoupling capacitor in the power distribution network, and reliable guidance is provided for power integrity design in the practical engineering.

5 citations

Proceedings ArticleDOI
, Jun Wang1, Hank Wu2
01 Jul 2019
TL;DR: A metric is presented base on the principal component analysis (PCA) to quantify the level of the nonlinearity of the high-speed links and results show that the metric can effectively capture the non linear severity of the links.
Abstract: With the data rate of high-speed links increasing, the impact of nonlinear factors becomes more and more prominent, which bring great signal integrity challenges to the analysis and design of high-speed links. However, there are two gaps in the study of the nonlinear behaviors of the high-speed links. One is that there is no simulation platform which can flexibly deal with different kinds of nonlinear behaviors. The other is that there is no metric which can quantify the level of the nonlinearity of the links. Aiming at these two problems, this paper first models a nonlinear high-speed link based on Simulink, which can flexibly adjust the nonlinear behaviors and analyze the impact of nonlinear behaviors on the performance of the high–speed links. Then a metric is presented base on the principal component analysis (PCA) to quantify the level of the nonlinearity of the high-speed links. Simulation results show that the metric can effectively capture the nonlinear severity of the links.

3 citations

##### Cited by
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Book
01 Jan 1985

224 citations

Proceedings Article
L.D. Smith
01 Jan 1999
TL;DR: The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.
Abstract: Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.

10 citations

Journal ArticleDOI
TL;DR: In this article, a semi-analytical method is proposed to evaluate the effectiveness of a decoupling capacitor on resonant power and ground planes, which yields the effective distance as well as the angle between a decouple capacitor and a power pin.
Abstract: A semi-analytical method is proposed to evaluate the effectiveness of a decoupling capacitor on resonant power and ground planes. New expressions are developed relating the pin impedance to relative placement of a capacitor with associated angular and distance parameters. To speed up the solution of resulting transcendental equations, a 2-D iterative technique is proposed, which yields the effective distance as well as the angle between a decoupling capacitor and a power pin. The partial derivatives of the corresponding Jacobian matrix are analytically derived. Numerical examples are presented to demonstrate the validity of the proposed method, which also investigates the effect of plane edges on pin impedance.

8 citations

Journal ArticleDOI
TL;DR: In this article, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation.
Abstract: In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network’s resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS’85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology.

8 citations

Journal ArticleDOI
TL;DR: Using the driving-point impedance (viewed from the device pin) as a metric, a new method is presented for the placement of decoupling capacitors in parallel-plate power ground pairs of high-speed circuits by formulated in the form of a transcendental function.
Abstract: With rapidly increasing switching speeds and surge current requirements, placement of local decoupling capacitors is becoming critically important in high-speed low-power designs. In this paper, utilizing the driving-point impedance (viewed from the device pin) as a metric, a new method is presented for the placement of decoupling capacitors in parallel-plate power ground pairs of high-speed circuits. In the proposed approach, instead of using the traditional trial-and-error method to identify an appropriate placement distance, the process is formulated in the form of a transcendental function. The resulting function is solved using Newton–Raphson (N-R) iterations to give a direct solution for the distance. Also, an analytical representation based on Hankel functions for the driving point impedance and its derivatives is developed to speed up the N-R iterations. The proposed method is validated by comparing the results with the full-wave electromagnetic simulations.

8 citations