Xu Li

Bio: Xu Li is an academic researcher from University of Electronic Science and Technology of China. The author has contributed to research in topics: MOSFET & Trench. The author has an hindex of 2, co-authored 9 publications receiving 32 citations.

Achieving Zero Switching Loss in Silicon Carbide MOSFET

Abstract: Due to the unipolar conduction mechanism, the switching loss of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor ( mosfet ) is reduced significantly when compared with silicon insulated gate bipolar transistor (IGBT). This enables the use of SiC mosfet in high-frequency application. However, the switching loss could still thermally limit the upper limit of the switching frequency. Further reduction of switching loss of SiC mosfet , therefore, remains an open challenge for higher frequency applications. Based on the in-depth revelation of device physics of the switching process, accurate switching loss model is established which highlights the dependence of the switching loss on the gate driving condition. With extreme fast gate driving condition, several loss limitations can be established. The minimum turn- on loss is the energy stored in the output capacitance and the minimum turn- off loss can approach zero or the so-called zero turn- off loss (ZTL). Furthermore, zero switching loss (ZSL) is achieved when utilizing zero-voltage switching turn- on and ZTL turn- off condition. With ZSL, the upper limit of the switching frequency is no long thermally limited which is verified by co-package experimental demonstration. We believe the trailblazing concepts of SiC mosfet switching loss will provide guiding principles for device innovation, package optimization, gate driver improvement, and current possible solutions toward higher frequency applications.

A Novel SiC MOSFET Embedding Low Barrier Diode With Enhanced Third Quadrant and Switching Performance

Abstract: A novel planar gate SiC MOSFET embedding low barrier diode (LBD-MOSFET) with improved third quadrant and switching performance is proposed and characterized in this letter. The LBD-MOSFET not only exhibits about 3 times lower diode turn on voltage than the body diode, but also successfully eliminates bipolar degradation phenomena. A low potential barrier for electrons transporting from JFET region to N+ source region is formed in LBD-MOSFET owing to the existence of the depletion charge in LBD base region. Meanwhile, the gate-to-drain charge ( ${Q}_{\text {gd}}){}$ and gate-to-drain capacitance ( ${C}_{\text {gd}}){}$ of LBD-MOSFET are significantly reduced by about $21\times $ and $15\times $ in comparison with the conventional MOSFET (C-MOSFET), due to the reduction of the overlapping area of the gate and drift region. Therefore, the obtained high frequency figures of merit (HF-FOM $1= {R}_{\text {on,sp}}\times {Q}_{\text {gd}}$ and HF-FOM $2= {R}_{\text {on,sp}}\times {C}_{\text {gd}}$ ) for the LBD-MOSFET are improved by about 13 times and 9 times compared with C-MOSFET. Furthermore, a compact potential barrier analytical model based on Poisson’s Law is developed to understand the origin of low potential barrier diode in SiC LBD-MOSFET. The overall enhanced performances suggest SiC LBD-MOSFET is an excellent choice for high frequency power electronic applications.

Short-Circuit Capability Prediction and Failure Mode of Asymmetric and Double Trench SiC MOSFETs

Abstract: In this article, short-circuit capability prediction and failure mode of 1200-V-class SiC MOSFET s with a double and asymmetric trench structure are proposed under single-pulse short-circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various dc bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in a short-circuit test. For asymmetric trench SiC MOSFET s, failure modes are gate damage at lower dc bus voltages and thermal runaway at higher dc bus voltages; whereas failure mode for double trench SiC MOSFET s is thermal runaway at all dc bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the dc bus voltage and peak short-circuit current of the device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFET s by the postdecapsulation.

Investigation of Surge Current Reliability of 1200V Planar and Trench SiC MOSFET

Abstract: The surge reliability of the body diode of 1200V planar SiC MOSFET and trench SiC MOFET is experimentally compared and analyzed in this paper. Two different failure modes of SiC MOSFET are reported and the physical mechanism of the failure is analyzed in detail. The maximum surge current and power density of planar SiC MOSFET is larger than trench SiC MOSFET. The planar MOSFET failed with a shortage between gate and source while the three terminals of trench MOSFET are shorted together after 112A surge current test. The analysis illustrates the failure of planar MOSFET may be associated with the interface traps and gate oxide traps above the channel while trench MOSFET failed due to thermal breakdown.

Switching Loss Model of SiC MOSFET Promoting High Frequency Applications

Abstract: In this work, the influence of parasitic capacitance on the switching loss of SiC MOSFET is investigated. The switching loss models considering $\boldsymbol{C}_{\mathbf{gd}}$ and $\boldsymbol{C}_{\mathbf{ds}}$ are obtained. Furthermore, the intrinsic minimum switching loss is identified as the energy dissipation resulting from the parasitic capacitance of the SiC MOSFET. Finally, the intrinsic losses of a number of commercial SiC MOSFETs are compared using the proposed model.

Soft-Switching Solid-State Transformer With Reduced Conduction Loss

Abstract: Solid-state transformers (SSTs) are a promising solution photovoltaic (PV), wind, traction, data center, battery energy storage system (BESS), and fast charging electric vehicle (EV) applications. The traditional SSTs are typically three-stage, i.e., hard-switching cascaded multilevel rectifiers and inverters with dual active bridge (DAB) converters, which leads to bulky passives, low efficiency, and high electromagnetic interference (EMI). This article proposes a new soft-switching solid-state transformer (S4T). The S4T has full-range zero-voltage switching (ZVS), electrolytic capacitor-less dc link, and controlled dv/dt , which reduces EMI. The S4T comprises two reverse-blocking current-source inverter (CSI) bridges, auxiliary branches for ZVS, and transformer magnetizing inductor as a reduced dc link with 60% ripple. Compared with the prior S4T, an effective change on the leakage inductance diode is made to reduce the number of the devices on the main power path by 20% for significant conduction loss saving and retain the same functionality of damping the resonance between the leakage and resonant capacitors and recycling trapped leakage energy. The conduction loss saving is crucial, being the dominating loss mechanism in SSTs. Importantly, the proposed single-stage SST not only holds the potential for high power density and high efficiency but also has full functionality, e.g., multiport dc loads integration, voltage regulation, and reactive power compensation, unlike the traditional single-stage matrix SST. The S4T can achieve single-stage isolated bidirectional dc–dc, ac–dc, dc–ac, or ac–ac conversion. It can also be configured input-series output-parallel (ISOP) in a modular way for medium-voltage (MV) grids. Hence, the S4T is a promising candidate for the SST. The full functionality, e.g., voltage buck–boost, multiport, etc., and the universality of the S4T for the dc–dc, dc–ac, and ac–ac conversion are verified through the simulations and experiments of two-port and three-port MV prototypes based on 3.3 kV SiC mosfet s in dc–dc, dc–ac, and ac–ac modes at 2 kV.

Power Cell Design and Assessment Methodology Based on a High-Current 10-kV SiC MOSFET Half-Bridge Module

Abstract: While 10-kV silicon-carbide (SiC) MOSFETs are gradually penetrating medium-voltage (MV) applications, intertwined challenges concerning high-voltage insulation, high ${dv}/{dt}$ , protections, and thermal management are simultaneously imposed to MV converters. For the modular multilevel converter, a systematical power cell design and assessment methodology (DAM) to tackle the unprecedented challenge synergy is essential and, yet, absent. Thereby, this article aims to develop a DAM based on a high-current 10-kV SiC MOSFET half-bridge module. An overall introduction of the power cell and a hierarchical DAM workflow is first presented, followed by the comprehensive component-level DAM with details on design challenges, solutions, assessment instruments, procedures, and test results. Subsequently, the DAM is expanded to the power cell level by exploring its safe operating area associated with switching frequency, power-processing capability, and temperature limit in various operation modes, which, in turn, validates the component designs and determines if they need iterations. Following the methodology, the power cell design is finalized, capable of continuous operation under 6 kV, 84-A rms, and 10 kHz, exhibiting 99.3% efficiency and transient immunity up to 100 V/ns.

Degradation of Hexagonal Silicon Carbide-based Bipolar Devices

Abstract: Silicon carbide displays multiple characteristics that make it ideally suited for efficient high voltage switching devices. However, the commercialization of this technology has been hampered by degradation of SiC p-n junctions due to the expansion of Shockleytype stacking faults. The faults gradually cover most of the junction area and impede current flow. This talk will on physics and materials science of this phenomenon including: properties of faults in hexagonal SiC polytypes and their bounding dislocations, mechanism and driving force for fault expansion, and their nucleation sites. The approaches to materials growth and processing leading to elimination of this effect will be discussed.

Current-Source Solid-State DC Transformer Integrating LVDC Microgrid, Energy Storage, and Renewable Energy Into MVDC Grid

Abstract: Solid-state dc transformer to integrate low-voltage dc (LVdc) microgrid, wind turbine (WT) generator, photovoltaic (PV), and energy storage (ES) into medium-voltage (MV) direct-current (MVdc) distribution grids is attractive. This article proposes current-source dc solid-state transformer (SST) for MVdc collection system in WT, PV, and ES farms or as an interface between the MVdc grid and the LVdc microgrid. Compared to conventional current-source converter (CSC) based SSTs, a switch reduction scheme on reverse-blocking device bridges is proposed to reduce device count and the number of devices on the dc-link current path. Importantly, the proposed switch reduction scheme is generic and can be applied to the dc ports of dc–ac, ac–dc, or dc–dc hard-switching or soft-switching CSC-based SSTs. Based on this scheme, the proposed current-source dc SSTs are derived, which have reduced electrolytic-capacitor-less dc-link. The proposed dc SSTs also achieve single-stage isolated dc–dc or dc–ac conversion, full-range zero-voltage switching (ZVS) for main switches, zero-current switching (ZCS) for resonant switches, and controlled $ dv/dt $ . The proposed dc SSTs, operating principles, predictive control method, the ZVS, and the controlled $ dv/dt $ under voltage buck-boost ranges are verified with MV simulations and an experimental prototype based on SiC mosfets , diodes, and a nanocrystalline transformer.

Current-Source Solid-State DC Transformer Integrating LVDC Microgrid, Energy Storage, and Renewable Energy Into MVDC Grid

Abstract: Solid-state dc transformer to integrate low-voltage dc (LVdc) microgrid, wind turbine (WT) generator, photovoltaic (PV), and energy storage (ES) into medium-voltage (MV) direct-current (MVdc) distribution grids is attractive. This article proposes current-source dc solid-state transformer (SST) for MVdc collection system in WT, PV, and ES farms or as an interface between the MVdc grid and the LVdc microgrid. Compared to conventional current-source converter (CSC) based SSTs, a switch reduction scheme on reverse-blocking device bridges is proposed to reduce device count and the number of devices on the dc-link current path. Importantly, the proposed switch reduction scheme is generic and can be applied to the dc ports of dc–ac, ac–dc, or dc–dc hard-switching or soft-switching CSC-based SSTs. Based on this scheme, the proposed current-source dc SSTs are derived, which have reduced electrolytic-capacitor-less dc-link. The proposed dc SSTs also achieve single-stage isolated dc–dc or dc–ac conversion, full-range zero-voltage switching (ZVS) for main switches, zero-current switching (ZCS) for resonant switches, and controlled $ dv/dt $ . The proposed dc SSTs, operating principles, predictive control method, the ZVS, and the controlled $ dv/dt $ under voltage buck-boost ranges are verified with MV simulations and an experimental prototype based on SiC mosfets , diodes, and a nanocrystalline transformer.