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Author

Xuefeng Gu

Other affiliations: Southeast University
Bio: Xuefeng Gu is an academic researcher from University of California, Los Angeles. The author has contributed to research in topics: CMOS & Physics. The author has an hindex of 5, co-authored 7 publications receiving 255 citations. Previous affiliations of Xuefeng Gu include Southeast University.

Papers
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Journal ArticleDOI
TL;DR: The prospect, including the potential to replace fluorescent/incandescent lighting devices as well as applications to flat panel displays and optoelectronics, and future challenges with regard to the design of metallic nanostructures and fabrication techniques are discussed.
Abstract: Light-emitting diodes [LEDs] are of particular interest recently as their performance is approaching fluorescent/incandescent tubes. Moreover, their energy-saving property is attracting many researchers because of the huge energy crisis we are facing. Among all methods intending to enhance the efficiency and intensity of a conventional LED, localized surface plasmon resonance is a promising way. The mechanism is based on the energy coupling effect between the emitted photons from the semiconductor and metallic nanoparticles fabricated by nanotechnology. In this review, we describe the mechanism of this coupling effect and summarize the common fabrication techniques. The prospect, including the potential to replace fluorescent/incandescent lighting devices as well as applications to flat panel displays and optoelectronics, and future challenges with regard to the design of metallic nanostructures and fabrication techniques are discussed.

149 citations

Journal ArticleDOI
TL;DR: In this article, a deep subwavelength terahertz plasmonic waveguide based on a graphene-metal hybrid structure is proposed, and a broadband mode confinement down to 1/100 of the free-space wavelength λ 0 with a loss of 0.6 dB/λ 0 is achieved when the intra-band electron relaxation time is 100 ps.
Abstract: A deep subwavelength terahertz plasmonic waveguide based on graphene-metal hybrid structure is proposed. A broadband mode confinement down to 1/100 of the free-space wavelength λ0 with a loss of 0.6 dB/λ0 can be achieved when the intra-band electron relaxation time is 100 ps. We show that very narrow slits with an appropriate periodicity created in the metal layer can serve as a grating to efficiently excite the surface plasmon-polariton mode with a normally incident terahertz beam, which can be further exploited for investigation of both interesting physics and innovative applications.

86 citations

Journal ArticleDOI
TL;DR: Experimental data from 22-nm silicon-on-insulator devices reveal that a charge-trap transistor possesses promising characteristics for implementing synapses in neural networks, such as very fine tunability, weight-dependent plasticity, and low power consumption.
Abstract: Unsupervised learning is demonstrated using a device ubiquitously found in today’s technology: a transistor with high- ${k}$ -metal gate. Specifically, the charge-trapping phenomenon in the high- ${k}$ gate dielectric is leveraged so that the device can be used as a non-volatile analog memory. Experimental data from 22-nm silicon-on-insulator devices reveal that a charge-trap transistor possesses promising characteristics for implementing synapses in neural networks, such as very fine tunability, weight-dependent plasticity, and low power consumption. A proof-of-concept winner-takes-all neural network is simulated based on experimental data and perfect clustering is achieved within tens of training cycles. This means that the network can be trained for multiple times, and a larger system can be built. The robustness of the procedure to the device variation is also discussed.

27 citations

Journal ArticleDOI
TL;DR: An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.
Abstract: An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog–digital interfaces. By implementing the sequential analog fabric, the engine’s mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem—classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.

26 citations

Journal ArticleDOI
TL;DR: A comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array reveals the promising future of using the CTT as a CMOS-only analog memory device.
Abstract: Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device characterization. In this article, we provide a comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array. It is found that, after programming, the channel current gradually increases to a higher level, and the shift is larger when the device is programmed to a higher threshold voltage. With this postprogramming current increase appropriately accounted for, individual devices can be programmed to an equivalent precision of five bits, and three bits can be achieved for devices in an array. Our results reveal the promising future of using the CTT as a CMOS-only analog memory device.

18 citations


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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you very much for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their favorite novels like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some malicious virus inside their laptop. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library saves in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Merely said, the design of analog cmos integrated circuits is universally compatible with any devices to read.

912 citations

Journal ArticleDOI
TL;DR: A comprehensive review on emerging artificial neuromorphic devices and their applications is offered, showing that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry.
Abstract: The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

373 citations

Journal ArticleDOI
TL;DR: In this paper, the design rules for achieving high-quality optical responses from metal nanoparticle arrays, nanofabrication advances that have enabled their production, and the theory that inspired their experimental realization are described.

316 citations

Journal ArticleDOI
TL;DR: Real-space imaging of acoustic THz plasmons in a graphene photodetector with split-gate architecture is demonstrated and nanoscale-resolved THz photocurrent near-field microscopy is introduced, where near- field excited GPs are detected thermoelectrically rather than optically.
Abstract: Near-field photocurrent nanoscopy is used for imaging strongly confined terahertz graphene plasmons with linear dispersion.

268 citations

Journal ArticleDOI
TL;DR: The state-of-the-art technology enabling bandwidth of GaN LEDs in the range of >400 MHz is explored and advances in key technologies, including advanced modulation, equalisation, and multiplexing that have enabled free-space VLC data rates beyond 10 Gb/s are outlined.
Abstract: The field of visible light communications (VLC) has gained significant interest over the last decade, in both fibre and free-space embodiments. In fibre systems, the availability of low cost plastic optical fibre (POF) that is compatible with visible data communications has been a key enabler. In free-space applications, the availability of hundreds of THz of the unregulated spectrum makes VLC attractive for wireless communications. This paper provides an overview of the recent developments in VLC systems based on gallium nitride (GaN) light-emitting diodes (LEDs), covering aspects from sources to systems. The state-of-the-art technology enabling bandwidth of GaN LEDs in the range of >400 MHz is explored. Furthermore, advances in key technologies, including advanced modulation, equalisation, and multiplexing that have enabled free-space VLC data rates beyond 10 Gb/s are also outlined.

208 citations