Y B Nithin Kumar

Bio: Y B Nithin Kumar is an academic researcher from National Institute of Technology Goa. The author has contributed to research in topics: CMOS & Flash ADC. The author has an hindex of 10, co-authored 53 publications receiving 259 citations. Previous affiliations of Y B Nithin Kumar include University of Pavia & National Institute of Technology Calicut.

A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core

Abstract: Reliability is a significant strategy concern for modern day multi core embedded systems. On chip communicating systems are vulnerable to permanent network faults and transient faults which might essentially affect the performance of the system. Targeting at fault tolerance solution for cores with faults in Network on Chip (NoC), this paper proposes an energy efficient fault tolerant NoC architecture using spare core. The proposed strategy comprises of finding smallest rectangular region to place the given application using a heuristic technique, and mapping vertices within the selected region, and selecting a region which results maximum overall performance and minimum communication energy. Spare core is placed within a region and connected to the vertices. Many application core graphs are used to evaluate the proposed technique. The simulation outcomes of many fault injection tests indicate that the proposed technique results in performance enhancement while also saving communication energy.

Design and analysis of multiplier using approximate 4-2 compressor

Abstract: Approximate computing has received significant attention as an attractive paradigm for error-tolerant applications to reduce the power consumption, delay and area with some trade-off in accuracy. This paper proposes the design of a novel approximate 4–2 compressor. A modified architecture of Dadda Multiplier is presented for the effective utilization of the proposed compressor and to reduce the error at the output. Through extensive experimental evaluation, the efficiency of the proposed compressor and multiplier are evaluated in a 45 nm standard CMOS technology and their parameters are compared with those of the state-of-the-art approximate multipliers. The results show that the proposed compressor accomplish a significant reduction in error rate compared to other approximate compressors available in the literature. In addition, the proposed multiplier shows 35%, 36% and 17% reduction in power consumption, delay and area respectively compared to those of exact multiplier. The effectiveness of multiplier is assessed by some of the image processing applications. On an average, the proposed multiplier processes images with 85% structural similarity compared to the exact output image.

Slew-rate and gain enhancement in two stage operational amplifiers

Abstract: A two stage op-amp with an effective technique to enhance slew-rate and gain is presented. The enhancement is provided by an auxiliary monitor circuit which is activated in slewing conditions, but can contribute to the gain in normal conditions. The amplifier, simulated in a 0.18 µm technology, achieves 74 dB DC gain, 160 MHz bandwidth and 26.8 V/µs slew-rate for a load capacitance of 1.75 pF with 362 µW power consumption, considering a supply voltage of 1.8 V.

Communication energy constrained spare core on NoC

Abstract: In multi-processor system on-chip, each processor produces and consumes high data. Hence, transporting of data becomes crucial in MPSOC. Therefore, Network on Chip (NoC) is preferred as an alternate medium because it provides good communication performance with comprehensive fast operation. This paper proposes the placement of spare core and its communication energy constraints while considering temporary and permanent fault occurrences in the core. We investigated energy metrics instead of spare core, bringing up lots of saving in terms of communication energy over the previous algorithms.

A fine grained position for modular core on NoC

Abstract: In this paper, the problem of spare core position when faults occur at core on Network on Chip (NoC) is proposed. More precisely, a fine grained spare core position is proposed, which goes for enhancing the entire system performance and communication energy consumption, while considering the occurrence of permanent, transient and intermittent faults in the system. This method finds the spare core near to perilous cores, as the key hypothetical involvement, the problem of spare core placement and its impact on system is discussed.

Design Of Analog Cmos Integrated Circuits

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Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications

Abstract: Approximate computing has emerged as a new paradigm for high-performance and energy-efficient design of circuits and systems. For the many approximate arithmetic circuits proposed, it has become critical to understand a design or approximation technique for a specific application to improve performance and energy efficiency with a minimal loss in accuracy. This article aims to provide a comprehensive survey and a comparative evaluation of recently developed approximate arithmetic circuits under different design constraints. Specifically, approximate adders, multipliers, and dividers are synthesized and characterized under optimizations for performance and area. The error and circuit characteristics are then generalized for different classes of designs. The applications of these circuits in image processing and deep neural networks indicate that the circuits with lower error rates or error biases perform better in simple computations, such as the sum of products, whereas more complex accumulative computations that involve multiple matrix multiplications and convolutions are vulnerable to single-sided errors that lead to a large error bias in the computed result. Such complex computations are more sensitive to errors in addition than those in multiplication, so a larger approximation can be tolerated in multipliers than in adders. The use of approximate arithmetic circuits can improve the quality of image processing and deep learning in addition to the benefits in performance and power consumption for these applications.

A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

Abstract: A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown.

ΣΔ Data Converters

Abstract: First written in 2003 for a book that was never published. Last updated on January 29, 2011. You can find the most recent version at www.designers-guide.org. Contact the author via email at monte.mar@comcast.net. Permission to make copies, either paper or electronic, of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage and that the copies are complete and unmodified. To distribute otherwise, to publish, to post on servers, or to distribute to lists, requires prior written permission.

Robust Color-to-Gray via Nonlinear Global Mapping

Abstract: This paper presents a fast color-to-gray conversion algorithm which robustly reproduces the visual appearance of a color image in grayscale. The conversion preserves feature discriminability and reasonable color ordering, while respecting the original lightness of colors, by simple optimization of a nonlinear global mapping. Experimental results show that our method produces convincing results for a variety of color images. We further extend the method to temporally coherent color-to-gray video conversion.