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Y. El-Mansy
Researcher at Intel
Publications - 5
Citations - 1495
Y. El-Mansy is an academic researcher from Intel. The author has contributed to research in topics: Electron mobility & Velocity saturation. The author has an hindex of 5, co-authored 5 publications receiving 1430 citations.
Papers
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Journal ArticleDOI
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,Mohsen Alavi,M. Buehler,R. Chau,S. Cea,Tahir Ghani,G. Glass,T. Hoffman,Chia-Hong Jan,C. Kenyon,Jason Klaus,K. Kuhn,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,B. Obradovic,Ramune Nagisetty,P. Nguyen,Swaminathan Sivakumar,R. Shaheed,Lucian Shifren,B. Tufts,S. Tyagi,M. Bohr,Y. El-Mansy +27 more
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Journal ArticleDOI
A logic nanotechnology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,S. Cea,R. Chau,G. Glass,T. Hoffman,Jason Klaus,Z. Ma,B. McIntyre,Anand Portland Murthy,B. Obradovic,Lucian Shifren,Swaminathan Sivakumar,S. Tyagi,Tahir Ghani,Kaizad Mistry,Mark T. Bohr,Y. El-Mansy +18 more
TL;DR: In this article, a tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility.
Journal ArticleDOI
Technology for advanced high-performance microprocessors
M.T. Bohr,Y. El-Mansy +1 more
TL;DR: In this paper, the authors describe the development of logic technologies that meet the density, performance, power, and manufacturing requirements for advanced high-performance microprocessors using planarized aluminum interconnects with high aspect ratios.
Journal ArticleDOI
MOS Device and technology constraints in VLSI
TL;DR: In this article, a number of performance limiters are pointed out and their effects on performance are evaluated for both p-and n-channel devices and future trends as impacted by them are explored.
Journal ArticleDOI
MOS Device and Technology Constraints in VLSI
TL;DR: In this article, a number of performance limiters are pointed out and their effects on performance are evaluated for both p- and n-charnel devices and future trends as impacted by these limiters were explored.